4 Commits

Author	SHA1	Message	Date
tangxifan	798e26e958	[Script] Add openfpga sdc generation script	2020-10-10 20:16:10 -06:00
tangxifan	3479502ab7	[Script] Update task template for testbench generation	2020-10-10 11:32:52 -06:00
tangxifan	a2b42c2e5f	[Script] Now use variables to redirect the output directory of Verilog/SDC files	2020-10-09 16:00:41 -06:00
tangxifan	64bbaf374d	[Flow] Add scripts to run OpenFPGA tasks	2020-10-09 14:49:54 -06:00