18 Commits

Author	SHA1	Message	Date
tangxifan	6fca7b9641	[Doc] Add figures about fle architecture v1.1	2020-12-04 09:27:11 -07:00
tangxifan	54eb5b469b	[Doc] Fix pin direction typo in I/O resource map	2020-11-28 20:13:05 -07:00
tangxifan	a4f6c34466	[Doc] Add images for multi-mode logic element architecture	2020-11-25 17:17:07 -07:00
tangxifan	fa9a3bd9f3	[Doc] Minor bug fix in the I/O mapping to wishbone	2020-11-20 18:26:41 -07:00
tangxifan	b2573bf242	[Doc] Update I/O resource documentation to synchronize the changes on wrapper	2020-11-20 18:24:29 -07:00
tangxifan	95107f9c7a	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
tangxifan	ca458b22f0	[Doc] Bug fix in io assignment	2020-11-18 20:31:30 -07:00
tangxifan	39b2b99ac2	[Doc] Update I/O switch by considering clock switches	2020-11-18 19:47:24 -07:00
tangxifan	655e19de6a	[Doc] Update I/O arrangement to avoid congestion in backend	2020-11-18 19:11:35 -07:00
tangxifan	2b0c5c67e9	[Doc] Update I/O arrangement to be consistent with new arch	2020-11-17 20:45:20 -07:00
tangxifan	b1ce66e8ce	[Doc] Update I/O circuitry details	2020-11-17 19:31:04 -07:00
tangxifan	b1dc28e605	[Doc] Patch typo in fpga I/O resource overview	2020-11-17 15:32:49 -07:00
tangxifan	52076b8714	[Doc] Add detailed architecture schematic	2020-11-17 11:44:57 -07:00
tangxifan	a2353355ec	[Doc] Update figures for I/O resources	2020-11-13 18:36:11 -07:00
tangxifan	8bae6bb893	[Doc] Update documentation about I/O resources	2020-11-13 17:24:43 -07:00
tangxifan	a018bd077a	[Doc] Add missing figures	2020-11-12 22:05:44 -07:00
tangxifan	67763c3464	[Doc] Update to latest architecture definition and device information	2020-11-12 21:59:14 -07:00
tangxifan	4897437c0d	[Doc] Add online documentation	2020-11-12 19:07:10 -07:00