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SOFA
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558 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

29 Commits

Author SHA1 Message Date
Tarachand Pagarani 9f7fb8a34d modify carry chain to change output mux 2020-11-30 07:08:09 -08:00
tangxifan c7ea3f3936 [Arch] Bug fix in the arch with reset and soft adder 2020-11-27 19:54:31 -07:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan 295df663bb [Arch] Add arch variant with soft adders 2020-11-27 15:57:05 -07:00
tangxifan f27424c803 [Arch] Bug fix in the architecture using reset 2020-11-27 15:04:19 -07:00
tangxifan c424c3d9a6 [Arch] Add a new variant with reset signals to FFs 2020-11-27 14:41:53 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
tangxifan 0fa3604b6c [Arch] Update arch to enable more routability in shift register mode 2020-11-25 17:04:08 -07:00
tangxifan 6aefa8077e [Arch] Critical patch on LE architecture which enables correct shift register connections 2020-11-25 16:40:54 -07:00
tangxifan a92b9ce482 [Arch] Test Quicklogic test architecture 2020-11-25 15:58:50 -07:00
tangxifan 55db5d5aaf [Arch] Revert to the classical pin location in vpr arch 2020-11-17 15:09:31 -07:00
tangxifan 22d0aaafeb [Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts 2020-11-17 11:47:47 -07:00
tangxifan 290b1f47a0 [Arch] Change I/O density to interface wishbone 2020-11-13 17:44:53 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan bbf871d22a [Arch] Limit shift register chain only to columns of clbs 2020-11-13 09:39:59 -07:00
tangxifan 5d3b08ada4 [Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric 2020-11-13 09:24:57 -07:00
tangxifan 16af5e6ad8 [Arch] Minor change to keep a regular arch in fle->lut connection 2020-11-09 15:52:46 -07:00
tangxifan 630c4060a8 [Arch] Detect some bugs (will not cause verification failed) in vpr arch 2020-11-09 15:12:00 -07:00
tangxifan 6811604e5c [Arch] Revert back to a lower Fc for area efficiency 2020-11-05 22:23:11 -07:00
tangxifan fe3bf8ba58 [Arch] Patch to have UNIQUE routing blocks 2020-11-05 22:20:51 -07:00
tangxifan 1892dd5205 [Arch] Minor patch on arch to force unique CBY 2020-11-05 21:55:43 -07:00
tangxifan 5b69b0a087 [Arch] Add the VPR architecture tuned for Caravel I/O interface 2020-11-05 09:43:38 -07:00
tangxifan c26f8a5aac [Arch] Add architecture files for embedded FPGA IP 2020-11-02 19:55:40 -07:00
tangxifan bff4fdfdc1 [Arch] Update pin equivalence for the non-LR non-adder k4 arch 2020-11-02 11:27:44 -07:00
tangxifan af4b89b37c [Arch] Bug fix in non-adder k4 arch 2020-10-24 12:00:20 -06:00
tangxifan bd834d4086 [Arch] Add a simplified k4 architecture without hard adders 2020-10-24 11:37:04 -06:00
tangxifan cee0fa601e [Documentation] Add README for subdirectories 2020-10-09 22:36:43 -06:00
tangxifan c5d6bcd15f [Architecture] Add VPR and OpenFPGA architecture description which is binded to skywater 130nm sclib 2020-10-09 14:33:42 -06:00