tangxifan
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8036d4f39d
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Merge pull request #29 from LNIS-Projects/ganesh_dev
Ganesh dev
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2020-11-19 14:44:09 -07:00 |
Ganesh Gore
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37e72cffb5
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[HDL] Updated wrapper generation script
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2020-11-18 23:15:26 -07:00 |
Ganesh Gore
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8818449c36
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Merge remote-tracking branch 'origin/xt_dev' into ganesh_dev
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2020-11-18 21:21:03 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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f927916946
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Merge pull request #28 from LNIS-Projects/xt_dev
Update I/O arrangement to avoid congestion in backend
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2020-11-18 20:52:24 -07:00 |
tangxifan
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014a6b56ce
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[HDL] Add clock switch to wrapper
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2020-11-18 20:50:10 -07:00 |
tangxifan
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33824bf179
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[HDL] Update caravel wrapper for new I/O assignment
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2020-11-18 20:44:54 -07:00 |
tangxifan
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ca458b22f0
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[Doc] Bug fix in io assignment
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2020-11-18 20:31:30 -07:00 |
tangxifan
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39b2b99ac2
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[Doc] Update I/O switch by considering clock switches
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2020-11-18 19:47:24 -07:00 |
tangxifan
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655e19de6a
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[Doc] Update I/O arrangement to avoid congestion in backend
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2020-11-18 19:11:35 -07:00 |
Ganesh Gore
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3daabd5448
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-11-18 17:55:52 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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720c65bc7f
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Merge pull request #27 from LNIS-Projects/xt_dev
Fabric Testbenches
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2020-11-18 16:28:24 -07:00 |
tangxifan
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f5d18d33ea
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[Testbench] Add scan-chain testbench for post-pnr verification
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2020-11-18 16:23:37 -07:00 |
tangxifan
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2c590e6fb2
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[Doc] Fix a typo in the resource count
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2020-11-18 16:21:17 -07:00 |
tangxifan
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439c73d211
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[Testbench] Add configuration chain test benches for pre- and post- pnr simulation
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2020-11-18 15:58:00 -07:00 |
tangxifan
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ce91890a0e
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[HDL] Now use a proper drive strength of 4 in the digital I/O cells
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2020-11-18 11:58:21 -07:00 |
tangxifan
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3ae41e2207
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[Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point
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2020-11-18 11:56:22 -07:00 |
tangxifan
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ea5c616339
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[Doc] Enhance I/O management guidelines
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2020-11-18 11:53:37 -07:00 |
tangxifan
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da0469728b
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[Doc] Add guidelines for setting unuses I/Os
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2020-11-18 11:50:21 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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4badd4dbae
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Merge pull request #26 from LNIS-Projects/xt_dev
Update I/O arrangement for Caravel Project Wrapper
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2020-11-18 11:35:43 -07:00 |
tangxifan
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4837e6d424
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[HDL] Remove out-of-data wrapper
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2020-11-18 11:30:53 -07:00 |
tangxifan
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a916ce7e03
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[HDL] Bug fix in the caravel fpga wrapper built with hd cell library
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2020-11-18 11:29:37 -07:00 |
tangxifan
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d36cb8abe7
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[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script
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2020-11-17 21:44:13 -07:00 |
tangxifan
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ed98aa27a8
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[Doc] Add I/O cell truth table
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2020-11-17 21:12:08 -07:00 |
tangxifan
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2b0c5c67e9
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[Doc] Update I/O arrangement to be consistent with new arch
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2020-11-17 20:45:20 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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2fe312258e
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Merge pull request #25 from LNIS-Projects/xt_dev
Create digital I/O Cell with protection circuitry
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2020-11-17 20:11:56 -07:00 |
tangxifan
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58440b8c42
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[HDL] Bug fix in I/O cell
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2020-11-17 20:03:20 -07:00 |
tangxifan
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1bfc793600
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[Arch] Bug fix due to the use of embedded I/O cell
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2020-11-17 19:55:04 -07:00 |
tangxifan
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6a27eca809
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[Arch] Update arch to use digital I/O circuitry
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2020-11-17 19:34:58 -07:00 |
tangxifan
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8803b30b26
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[HDL] Rename por of I/O cell to be consistent with documentation
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2020-11-17 19:33:53 -07:00 |
tangxifan
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b1ce66e8ce
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[Doc] Update I/O circuitry details
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2020-11-17 19:31:04 -07:00 |
tangxifan
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5415af07cc
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[HDL] Add digitial I/O with protection circuitry
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2020-11-17 19:17:48 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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6068eb9b01
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Merge pull request #24 from LNIS-Projects/xt_dev
Add Post-PnR Testbench for AND2_LATCH Benchmark
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2020-11-17 17:43:35 -07:00 |
tangxifan
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0681e34a1b
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[Testbench] Add post PnR testbench for and2_latch benchmark
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2020-11-17 17:39:53 -07:00 |
tangxifan
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6cdf477bfc
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[Doc] Format documentation organization and text
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2020-11-17 17:35:07 -07:00 |
tangxifan
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b1dc28e605
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[Doc] Patch typo in fpga I/O resource overview
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2020-11-17 15:32:49 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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3c898ae5c8
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Merge pull request #23 from LNIS-Projects/xt_dev
Misc Updates: OpenFPGA scripts, Benchmarks and Architecture
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2020-11-17 15:21:10 -07:00 |
tangxifan
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55db5d5aaf
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[Arch] Revert to the classical pin location in vpr arch
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2020-11-17 15:09:31 -07:00 |
tangxifan
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86bb530709
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[Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC
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2020-11-17 15:03:10 -07:00 |
tangxifan
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cbd9239e41
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[Script] Add custom simulation settings for the Skywater 130nm eFPGA fabric
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2020-11-17 14:57:23 -07:00 |
tangxifan
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a97598cef9
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[Script] Patch example openfpga shell script to manage clock routing in VPR
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2020-11-17 14:27:14 -07:00 |
tangxifan
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0e2ee8a0cc
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[Script] Add benchmarks to OpenFPGA task run
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2020-11-17 14:01:48 -07:00 |
tangxifan
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75db7b255b
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[Benchmark] Add micro benchmarks
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2020-11-17 13:55:47 -07:00 |
tangxifan
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39aa11c42c
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[Script] Update OpenFPGA task run configuration for pre-pnr files
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2020-11-17 13:46:25 -07:00 |
tangxifan
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804d96bf50
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[Testbench] Rename post-pnr testbenches to dedicated directories
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2020-11-17 13:45:55 -07:00 |
tangxifan
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efda8e0f73
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[Script] Update task run configuration in output directory
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2020-11-17 13:21:26 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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ffc072f36e
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Merge pull request #22 from LNIS-Projects/xt_dev
Misc Updates: Architecture, Post-PnR Testbench and Documentation
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2020-11-17 13:13:26 -07:00 |
tangxifan
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0d62af2980
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[Doc] Add missing files about clb architecture
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2020-11-17 12:04:38 -07:00 |
tangxifan
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22d0aaafeb
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[Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts
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2020-11-17 11:47:47 -07:00 |
tangxifan
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52076b8714
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[Doc] Add detailed architecture schematic
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2020-11-17 11:44:57 -07:00 |
tangxifan
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a1bb7a3ddc
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[Testbench] Update testbench for post-pnr
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2020-11-17 11:42:35 -07:00 |