63 Commits

Author	SHA1	Message	Date
tangxifan	a916ce7e03	[HDL] Bug fix in the caravel fpga wrapper built with hd cell library	2020-11-18 11:29:37 -07:00
tangxifan	d36cb8abe7	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00
tangxifan	58440b8c42	[HDL] Bug fix in I/O cell	2020-11-17 20:03:20 -07:00
tangxifan	8803b30b26	[HDL] Rename por of I/O cell to be consistent with documentation	2020-11-17 19:33:53 -07:00
tangxifan	5415af07cc	[HDL] Add digitial I/O with protection circuitry	2020-11-17 19:17:48 -07:00
tangxifan	625ad5e9c6	[HDL] Alpha version of behavioral-level Verilog for SoC wrapper	2020-11-13 18:34:40 -07:00
tangxifan	80655c5869	[HDL] Digital I/O of embedded FPGA is now lib independent	2020-11-13 10:00:30 -07:00
tangxifan	5f02463098	[HDL] Update wrapper for caravel SoC interface	2020-11-12 19:06:49 -07:00
tangxifan	ae97e4424d	[HDL] Add wrapper for Caravel interface	2020-11-07 22:42:29 -07:00
tangxifan	e952eb951d	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00
tangxifan	64d1113461	[HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel	2020-11-05 10:18:52 -07:00
tangxifan	8702073354	[Doc] Add readme for HDL directory	2020-11-03 09:23:33 -07:00
tangxifan	12881d7a31	[HDL] Move verilog wrapper to HDL directory	2020-11-03 09:19:43 -07:00