7 Commits

Author	SHA1	Message	Date
Ganesh Gore	f385c0ca11	[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist	2020-12-02 01:43:05 -07:00
tangxifan	78addbe294	[HDL] Name fix to be compatible with testbench generation	2020-11-29 21:01:44 -07:00
tangxifan	899018d503	[HDL] Bug fix in wrapper template	2020-11-29 12:38:25 -07:00
tangxifan	ea758cd5b1	[HDL] Update wrapper template as most codes can be auto-generated	2020-11-29 12:36:23 -07:00
tangxifan	b08b77994c	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
tangxifan	6fa5e935fa	[HDL] Update wrapper generator to use tri-state buffer for outputs	2020-11-19 17:14:50 -07:00
Ganesh Gore	37e72cffb5	[HDL] Updated wrapper generation script	2020-11-18 23:15:26 -07:00