38 Commits

Author	SHA1	Message	Date
tangxifan	f5c1d9c0a0	[Arch] enable local encoders	2020-12-06 01:40:21 -07:00
tangxifan	004f9dbcca	[Arch] Bug fix in new arch	2020-12-06 01:40:21 -07:00
tangxifan	4ddc6955a3	[Arch] Add architecture using custom cells	2020-12-06 01:40:21 -07:00
Laboratory for Nano Integrated Systems (LNIS)	f4397e1656	Merge pull request #47 from LNIS-Projects/xt_dev ... Bug fix in the arch port naming	2020-11-30 18:23:38 -07:00
tangxifan	be9399a016	[Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA	2020-11-30 17:58:56 -07:00
Tarachand Pagarani	9f7fb8a34d	modify carry chain to change output mux	2020-11-30 07:08:09 -08:00
tangxifan	14c21378b8	[Arch] Add new architecture using reset and softadder	2020-11-27 18:12:06 -07:00
tangxifan	efab96d2dd	[Arch] Bug fix in softadder architecture	2020-11-27 16:36:31 -07:00
tangxifan	295df663bb	[Arch] Add arch variant with soft adders	2020-11-27 15:57:05 -07:00
tangxifan	c424c3d9a6	[Arch] Add a new variant with reset signals to FFs	2020-11-27 14:41:53 -07:00
tangxifan	864ed26c9a	[Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture	2020-11-27 10:11:40 -07:00
tangxifan	a92b9ce482	[Arch] Test Quicklogic test architecture	2020-11-25 15:58:50 -07:00
tangxifan	3ae41e2207	[Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point	2020-11-18 11:56:22 -07:00
tangxifan	1bfc793600	[Arch] Bug fix due to the use of embedded I/O cell	2020-11-17 19:55:04 -07:00
tangxifan	6a27eca809	[Arch] Update arch to use digital I/O circuitry	2020-11-17 19:34:58 -07:00
tangxifan	be33082faf	[Arch] Remove out-of-data architectures	2020-11-13 09:50:45 -07:00
tangxifan	bbf871d22a	[Arch] Limit shift register chain only to columns of clbs	2020-11-13 09:39:59 -07:00
tangxifan	5d3b08ada4	[Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric	2020-11-13 09:24:57 -07:00
tangxifan	7dafb7e3b2	[Arch] Use global clock from tile port in caravel architecture	2020-11-11 19:43:24 -07:00
tangxifan	11ee81f8c4	[Arch] Bug fix in the caravel arch	2020-11-08 14:25:38 -07:00
tangxifan	8d84d83eab	[Arch] Use single-output DFF to further compress area	2020-11-06 11:47:31 -07:00
tangxifan	6b474ce422	[Arch] Patch openfpga arch for new syntax on I/O	2020-11-05 10:37:37 -07:00
tangxifan	a25b8252f3	[Arch] Add openfpga arch template for the caravel	2020-11-05 10:20:54 -07:00
tangxifan	1264054cab	[Arch] Bug fix in netlist path	2020-11-03 09:57:25 -07:00
tangxifan	48d8f8b664	[Arch] Same patch on the scff on another arch	2020-11-03 09:54:30 -07:00
tangxifan	533a6ab90f	[Arch] Use an exact fit scan-chain flip-flop in the architectures	2020-11-03 09:53:16 -07:00
tangxifan	b5c781f555	[Arch] Patch the HDL netlist name to differetiate between cell types	2020-11-03 09:17:22 -07:00
tangxifan	40ca8dfbe3	[Arch] Update architecture files to use the wrapper files	2020-11-03 09:14:47 -07:00
tangxifan	c26f8a5aac	[Arch] Add architecture files for embedded FPGA IP	2020-11-02 19:55:40 -07:00
tangxifan	bff4fdfdc1	[Arch] Update pin equivalence for the non-LR non-adder k4 arch	2020-11-02 11:27:44 -07:00
tangxifan	23ac6af11f	[Arch] Bug fix on the wrong verilog netlist path	2020-11-01 15:45:41 -07:00
tangxifan	eaf5ba6074	[Arch] Add openfpga arch for non-adder k4 vpr arch	2020-10-24 11:44:41 -06:00
tangxifan	5e6a6d1e53	[Architecture] Add a set of openfpga architectures using different Skywater Foundry standard cells	2020-10-14 09:11:05 -06:00
tangxifan	14050bba26	[Architecture] Add OpenFPGA architecture which is binded to the open-source ms sclib	2020-10-10 19:16:35 -06:00
tangxifan	cee0fa601e	[Documentation] Add README for subdirectories	2020-10-09 22:36:43 -06:00
tangxifan	8b5a17457c	[Architecture] bug fix in openfpga arch	2020-10-09 20:30:51 -06:00
tangxifan	0053c57954	[Arch] Update architecture file	2020-10-09 18:32:31 -06:00
tangxifan	069c36cbfc	[Architecture] Create template architecture for openfpga	2020-10-09 17:28:14 -06:00