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Added reset and prog_reset feedthrough

This commit is contained in:
Ganesh Gore 2023-03-01 20:41:37 -07:00
parent 8d120b23b6
commit fc87f9a977
12 changed files with 963 additions and 270 deletions
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37
SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
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@ -193,6 +193,21 @@ def main():
filename=f"{RELEASE_DIR}/rpts/pre_pnr/shaping.txt",
)
# Signal pins
fpga.fix_grid_pin_names(
regex=r".*__pin_(reset|prog_reset)_0_", module="grid_*")
fpga.fix_grid_pin_names(
regex=r".*__pin_(reset|prog_reset)_0_", module="cbx*")
# For clock signals
fpga.fix_grid_pin_names(
regex=r".*__pin_(clk.*)_",
module="grid_*",
name_map=lambda x: x.replace("_", ""),
)
fpga.fix_grid_pin_names(
regex=r".*__pin_(clk.*)_", module="cb*", name_map=lambda x: x.replace("_", "")
)
filename = SVG_DIR + f"{PROJ_NAME}_raw_floorplan.svg"
save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
@ -218,15 +233,6 @@ def main():
shapes[module]["PLACEMENT"][1] += 1
fpga.create_placement()
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Feedthrough generation
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
instance_map = [[0 for _ in range(FPGA_HEIGHT + 1)]
for _ in range(FPGA_WIDTH + 1)]
for inst in fpga.top_module.get_instances():
_, x, _, y, _ = inst.name.rsplit("_", 4)
instance_map[int(x)][int(y)] = inst.name
# create_global_feedthrough(fpga, "reset", instance_map)
filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg"
save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
@ -234,8 +240,19 @@ def main():
# Create tiles
fpga.register_tile_generator(Tile02)
fpga.create_tiles()
save_netlist(fpga)
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Feedthrough generation
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
instance_map = [[0 for _ in range(FPGA_HEIGHT + 2)]
for _ in range(FPGA_WIDTH + 2)]
for inst in fpga.top_module.get_instances():
_, x, _, y, _ = inst.name.rsplit("_", 4)
instance_map[int(x)][int(y)] = inst.name
create_global_feedthrough(fpga, "reset", instance_map)
create_global_feedthrough(fpga, "prog_reset", instance_map)
save_netlist(fpga)
filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg"
save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
# pickle.dump(

990
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
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File diff suppressed because it is too large Load Diff

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v
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@ -3,10 +3,10 @@
module grid_clb
(
ccff_head,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
clk0,
prog_clk,
prog_reset,
reset,
right_width_0_height_0_subtile_0__pin_I4_0_,
right_width_0_height_0_subtile_0__pin_I4_1_,
right_width_0_height_0_subtile_0__pin_I4i_0_,
@ -66,10 +66,10 @@ module grid_clb
);
input ccff_head;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input clk0;
input prog_clk;
input prog_reset;
input reset;
input right_width_0_height_0_subtile_0__pin_I4_0_;
input right_width_0_height_0_subtile_0__pin_I4_1_;
input right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -132,10 +132,10 @@ module grid_clb
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
wire ccff_head;
wire ccff_tail;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire clk0;
wire prog_clk;
wire prog_reset;
wire reset;
wire right_width_0_height_0_subtile_0__pin_I4_0_;
wire right_width_0_height_0_subtile_0__pin_I4_1_;
wire right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -209,9 +209,9 @@ module grid_clb
.clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}),
.clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}),
.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
.clb_clk(clk0),
.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
.clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
.clb_reset(reset),
.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
.prog_clk(prog_clk),
.prog_reset(prog_reset),

9
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v
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@ -6,7 +6,8 @@ module bottom_left_tile
chanx_right_in,
chany_top_in,
prog_clk,
prog_reset,
prog_reset_top_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -24,7 +25,8 @@ module bottom_left_tile
input [29:0]chanx_right_in;
input [29:0]chany_top_in;
input prog_clk;
input prog_reset;
input prog_reset_top_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -45,6 +47,8 @@ module bottom_left_tile
wire [29:0]chany_top_out;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -54,6 +58,7 @@ module bottom_left_tile
wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
sb_0__0_ sb_0__0_
(
.ccff_head(ccff_head),

9
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v
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@ -10,7 +10,8 @@ module bottom_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
prog_reset_top_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -44,7 +45,8 @@ module bottom_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input prog_reset_top_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -88,6 +90,8 @@ module bottom_tile
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -105,6 +109,7 @@ module bottom_tile
wire top_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
cbx_1__0_ cbx_1__0_
(
.ccff_head(ccff_head),

45
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v
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@ -10,7 +10,12 @@ module left_tile
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
prog_reset_bottom_in,
prog_reset_left_in,
prog_reset_top_in,
reset_bottom_in,
reset_right_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -30,6 +35,11 @@ module left_tile
chany_top_out_0,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
prog_reset_bottom_out,
prog_reset_right_out,
prog_reset_top_out,
reset_bottom_out,
reset_top_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
@ -44,7 +54,12 @@ module left_tile
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input prog_reset_bottom_in;
input prog_reset_left_in;
input prog_reset_top_in;
input reset_bottom_in;
input reset_right_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -64,6 +79,11 @@ module left_tile
output [29:0]chany_top_out_0;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output prog_reset_bottom_out;
output prog_reset_right_out;
output prog_reset_top_out;
output reset_bottom_out;
output reset_top_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
@ -87,6 +107,17 @@ module left_tile
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire prog_reset_bottom_out;
wire prog_reset_left_in;
wire prog_reset_right_out;
wire prog_reset_top_in;
wire prog_reset_top_out;
wire reset_bottom_in;
wire reset_bottom_out;
wire reset_right_in;
wire reset_top_in;
wire reset_top_out;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -104,6 +135,16 @@ module left_tile
wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_bottom_in;
assign prog_reset_top_in = prog_reset_left_in;
assign prog_reset_right_out = prog_reset;
assign prog_reset_top_out = prog_reset_right_out;
assign prog_reset_bottom_in = prog_reset_top_in;
assign prog_reset_bottom_out = prog_reset_top_out;
assign reset_top_out = reset_bottom_in;
assign reset_top_in = reset_right_in;
assign reset_bottom_in = reset_top_in;
assign reset_bottom_out = reset_top_out;
cby_0__1_ cby_0__1_
(
.ccff_head_0(ccff_head_0),

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
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@ -8,12 +8,12 @@ module right_tile
chanx_left_in,
chany_bottom_in,
chany_top_in_0,
clk0,
gfpga_pad_io_soc_in,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
prog_clk,
prog_reset,
reset,
scan_enable,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
@ -69,12 +69,12 @@ module right_tile
input [29:0]chanx_left_in;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input clk0;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input prog_clk;
input prog_reset;
input reset;
input scan_enable;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
@ -160,6 +160,7 @@ module right_tile
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire clk0;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
@ -180,14 +181,13 @@ module right_tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_inpad_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire prog_clk;
wire prog_reset;
wire reset;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -288,10 +288,10 @@ module right_tile
grid_clb grid_clb_8__1_
(
.ccff_head(ccff_tail_0_0),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.clk0(clk0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.reset(reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),

64
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v
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@ -8,10 +8,14 @@ module tile
chanx_right_in_0,
chany_bottom_in,
chany_top_in_0,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
clk0,
prog_clk,
prog_reset,
prog_reset_bottom_in,
prog_reset_left_in,
prog_reset_top_in,
reset_bottom_in,
reset_right_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -41,6 +45,12 @@ module tile
chanx_right_out_0,
chany_bottom_out,
chany_top_out_0,
prog_reset_bottom_out,
prog_reset_right_out,
prog_reset_top_out,
reset_bottom_out,
reset_left_out,
reset_top_out,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
@ -65,10 +75,14 @@ module tile
input [29:0]chanx_right_in_0;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input clk0;
input prog_clk;
input prog_reset;
input prog_reset_bottom_in;
input prog_reset_left_in;
input prog_reset_top_in;
input reset_bottom_in;
input reset_right_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -98,6 +112,12 @@ module tile
output [29:0]chanx_right_out_0;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out_0;
output prog_reset_bottom_out;
output prog_reset_right_out;
output prog_reset_top_out;
output reset_bottom_out;
output reset_left_out;
output reset_top_out;
output right_width_0_height_0_subtile_0__pin_O_10_;
output right_width_0_height_0_subtile_0__pin_O_11_;
output right_width_0_height_0_subtile_0__pin_O_12_;
@ -152,6 +172,7 @@ module tile
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire clk0;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -168,10 +189,21 @@ module tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire prog_reset_bottom_out;
wire prog_reset_left_in;
wire prog_reset_right_out;
wire prog_reset_top_in;
wire prog_reset_top_out;
wire reset;
wire reset_bottom_in;
wire reset_bottom_out;
wire reset_left_out;
wire reset_right_in;
wire reset_top_in;
wire reset_top_out;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -209,6 +241,18 @@ module tile
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
assign prog_reset = prog_reset_bottom_in;
assign prog_reset_top_in = prog_reset_left_in;
assign prog_reset_right_out = prog_reset;
assign prog_reset_top_out = prog_reset_right_out;
assign prog_reset_bottom_in = prog_reset_top_in;
assign prog_reset_bottom_out = prog_reset_top_out;
assign reset = reset_bottom_in;
assign reset_top_out = reset_left_out;
assign reset_left_out = reset;
assign reset_top_in = reset_right_in;
assign reset_bottom_in = reset_top_in;
assign reset_bottom_out = reset_top_out;
cbx_1__1_ cbx_1__1_
(
.ccff_head(ccff_tail_2),
@ -266,10 +310,10 @@ module tile
grid_clb grid_clb_1__1_
(
.ccff_head(ccff_tail_1),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.clk0(clk0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.reset(reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
View File

@ -6,13 +6,13 @@ module top_right_tile
ccff_head_1,
chanx_left_in,
chany_bottom_in,
clk0,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_in_0,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
prog_clk,
prog_reset,
reset,
scan_enable,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
@ -58,13 +58,13 @@ module top_right_tile
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chany_bottom_in;
input clk0;
input [3:0]gfpga_pad_io_soc_in;
input [3:0]gfpga_pad_io_soc_in_0;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input prog_clk;
input prog_reset;
input reset;
input scan_enable;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
@ -143,6 +143,7 @@ module top_right_tile
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire clk0;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_dir_0;
wire [3:0]gfpga_pad_io_soc_in;
@ -166,14 +167,13 @@ module top_right_tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_inpad_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire prog_clk;
wire prog_reset;
wire reset;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -270,10 +270,10 @@ module top_right_tile
grid_clb grid_clb_8__8_
(
.ccff_head(ccff_tail_0_0),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.clk0(clk0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.reset(reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
View File

@ -7,12 +7,12 @@ module top_tile
chanx_left_in,
chanx_right_in_0,
chany_bottom_in,
clk0,
gfpga_pad_io_soc_in,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
prog_clk,
prog_reset,
reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -66,12 +66,12 @@ module top_tile
input [29:0]chanx_left_in;
input [29:0]chanx_right_in_0;
input [29:0]chany_bottom_in;
input clk0;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input prog_clk;
input prog_reset;
input reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -158,6 +158,7 @@ module top_tile
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire clk0;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
@ -178,10 +179,9 @@ module top_tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire prog_clk;
wire prog_reset;
wire reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -280,10 +280,10 @@ module top_tile
grid_clb grid_clb_1__8_
(
.ccff_head(ccff_tail_1),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.clk0(clk0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.reset(reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),

8
SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt Normal file
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@ -0,0 +1,8 @@
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
Module | In | Out
Module | L R T B | L R T B
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
bottom_left_tile | - - 1 - | - - - -
bottom_tile | - - 7 - | - - - -
left_tile | 1 - 3 3 | - 1 3 4
tile | 7 - 21 21 | - 6 21 28

7
SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt
View File

@ -2,6 +2,7 @@
Module | In | Out
Module | L R T B | L R T B
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
cbx_1__8_ | - - - 7 | - - - -
cby_1__1_ | - 7 28 14 | 6 - 21 28
cby_8__1_ | - 1 4 3 | 1 - 3 4
bottom_left_tile | - - 1 - | - - - -
bottom_tile | - - 7 - | - - - -
left_tile | - 1 3 3 | - - 3 4
tile | - 7 21 21 | 7 - 21 28