From fc87f9a9775df0c219e7d2c1a5273dd3010c93b3 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 1 Mar 2023 20:41:37 -0700 Subject: [PATCH] Added reset and prog_reset feedthrough --- .../CommonFiles/restructure_fabric_sofa_a.py | 37 +- .../FPGA88_SOFA_A_verilog/SRC/fpga_top.v | 990 ++++++++++++++---- .../SRC/submodules/grid_clb.v | 16 +- .../SRC/tile/bottom_left_tile.v | 9 +- .../SRC/tile/bottom_tile.v | 9 +- .../SRC/tile/left_tile.v | 45 +- .../SRC/tile/right_tile.v | 16 +- .../FPGA88_SOFA_A_verilog/SRC/tile/tile.v | 64 +- .../SRC/tile/top_right_tile.v | 16 +- .../FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v | 16 +- .../release/rpts/pre_pnr/prog_reset_ports.txt | 8 + .../release/rpts/pre_pnr/reset_ports.txt | 7 +- 12 files changed, 963 insertions(+), 270 deletions(-) create mode 100644 SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt diff --git a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py index 4172e4a..fef699e 100644 --- a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py +++ b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py @@ -193,6 +193,21 @@ def main(): filename=f"{RELEASE_DIR}/rpts/pre_pnr/shaping.txt", ) + # Signal pins + fpga.fix_grid_pin_names( + regex=r".*__pin_(reset|prog_reset)_0_", module="grid_*") + fpga.fix_grid_pin_names( + regex=r".*__pin_(reset|prog_reset)_0_", module="cbx*") + # For clock signals + fpga.fix_grid_pin_names( + regex=r".*__pin_(clk.*)_", + module="grid_*", + name_map=lambda x: x.replace("_", ""), + ) + fpga.fix_grid_pin_names( + regex=r".*__pin_(clk.*)_", module="cb*", name_map=lambda x: x.replace("_", "") + ) + filename = SVG_DIR + f"{PROJ_NAME}_raw_floorplan.svg" save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) @@ -218,15 +233,6 @@ def main(): shapes[module]["PLACEMENT"][1] += 1 fpga.create_placement() - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - # Feedthrough generation - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - instance_map = [[0 for _ in range(FPGA_HEIGHT + 1)] - for _ in range(FPGA_WIDTH + 1)] - for inst in fpga.top_module.get_instances(): - _, x, _, y, _ = inst.name.rsplit("_", 4) - instance_map[int(x)][int(y)] = inst.name - # create_global_feedthrough(fpga, "reset", instance_map) filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg" save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) @@ -234,8 +240,19 @@ def main(): # Create tiles fpga.register_tile_generator(Tile02) fpga.create_tiles() - save_netlist(fpga) + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Feedthrough generation + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + instance_map = [[0 for _ in range(FPGA_HEIGHT + 2)] + for _ in range(FPGA_WIDTH + 2)] + for inst in fpga.top_module.get_instances(): + _, x, _, y, _ = inst.name.rsplit("_", 4) + instance_map[int(x)][int(y)] = inst.name + create_global_feedthrough(fpga, "reset", instance_map) + create_global_feedthrough(fpga, "prog_reset", instance_map) + + save_netlist(fpga) filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg" save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) # pickle.dump( diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v index db6e0a4..a00d160 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v @@ -4275,7 +4275,9 @@ module fpga_top wire isol_n; wire prog_clk; wire prog_reset; + wire [63:0]prog_reset_ft; wire reset; + wire [63:0]reset_ft; wire sb_0__0__0_ccff_tail; wire [0:29]sb_0__0__0_chanx_right_out; wire [0:29]sb_0__0__0_chany_top_out; @@ -4647,13 +4649,16 @@ module fpga_top wire [0:29]sb_8__8__0_chany_bottom_out; wire scan_enable; +assign prog_reset_ft[0] = prog_reset; +assign reset_ft[0] = reset; bottom_left_tile tile_1__1_ ( .ccff_head(grid_io_left_left_1_ccff_tail), .chanx_right_in(cbx_1__0__0_chanx_left_out), .chany_top_in(cby_0__1__0_chany_bottom_out), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[4]), + .reset_top_in(reset_ft[63]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4676,7 +4681,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[96:99]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[3]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[62]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4696,6 +4706,11 @@ module fpga_top .chany_top_out_0(sb_0__1__0_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[96:99]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[96:99]), + .prog_reset_bottom_out(prog_reset_ft[4]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[63]), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4711,7 +4726,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[100:103]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[2]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[61]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4731,6 +4751,11 @@ module fpga_top .chany_top_out_0(sb_0__1__1_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[100:103]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[100:103]), + .prog_reset_bottom_out(prog_reset_ft[3]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[62]), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4746,7 +4771,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[104:107]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[1]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[60]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4766,6 +4796,11 @@ module fpga_top .chany_top_out_0(sb_0__1__2_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[104:107]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[104:107]), + .prog_reset_bottom_out(prog_reset_ft[2]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[61]), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4781,7 +4816,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[108:111]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[0]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[56]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4801,6 +4841,11 @@ module fpga_top .chany_top_out_0(sb_0__1__3_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[108:111]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[108:111]), + .prog_reset_bottom_out(prog_reset_ft[1]), + .prog_reset_right_out(prog_reset_ft[8]), + .prog_reset_top_out(prog_reset_ft[5]), + .reset_bottom_out(reset_ft[60]), + .reset_top_out(reset_ft[57]), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4816,7 +4861,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[112:115]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[5]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[57]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4836,6 +4886,11 @@ module fpga_top .chany_top_out_0(sb_0__1__4_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[112:115]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[112:115]), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[6]), + .reset_bottom_out(), + .reset_top_out(reset_ft[58]), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4851,7 +4906,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[116:119]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[6]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[58]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4871,6 +4931,11 @@ module fpga_top .chany_top_out_0(sb_0__1__5_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[116:119]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[116:119]), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[7]), + .reset_bottom_out(), + .reset_top_out(reset_ft[59]), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4886,7 +4951,12 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[120:123]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[7]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[59]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4906,6 +4976,11 @@ module fpga_top .chany_top_out_0(sb_0__1__6_chany_top_out), .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[120:123]), .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[120:123]), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4920,7 +4995,7 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[124:127]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), @@ -4954,7 +5029,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[92:95]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[12]), + .reset_top_in(reset_ft[55]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -4987,10 +5063,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__7_chanx_left_out), .chany_bottom_in(sb_1__0__0_chany_top_out), .chany_top_in_0(cby_1__1__1_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[11]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[54]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5020,6 +5100,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__0_chanx_right_out), .chany_bottom_out(cby_1__1__0_chany_bottom_out), .chany_top_out_0(sb_1__1__0_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[12]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[55]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5045,10 +5131,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__8_chanx_left_out), .chany_bottom_in(sb_1__1__0_chany_top_out), .chany_top_in_0(cby_1__1__2_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[10]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[53]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5078,6 +5168,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__1_chanx_right_out), .chany_bottom_out(cby_1__1__1_chany_bottom_out), .chany_top_out_0(sb_1__1__1_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[11]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[54]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5103,10 +5199,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__9_chanx_left_out), .chany_bottom_in(sb_1__1__1_chany_top_out), .chany_top_in_0(cby_1__1__3_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[9]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[52]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5136,6 +5236,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__2_chanx_right_out), .chany_bottom_out(cby_1__1__2_chany_bottom_out), .chany_top_out_0(sb_1__1__2_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[10]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[53]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5161,10 +5267,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__10_chanx_left_out), .chany_bottom_in(sb_1__1__2_chany_top_out), .chany_top_in_0(cby_1__1__4_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[8]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[48]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5194,6 +5304,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__3_chanx_right_out), .chany_bottom_out(cby_1__1__3_chany_bottom_out), .chany_top_out_0(sb_1__1__3_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[9]), + .prog_reset_right_out(prog_reset_ft[16]), + .prog_reset_top_out(prog_reset_ft[13]), + .reset_bottom_out(reset_ft[52]), + .reset_left_out(reset_ft[56]), + .reset_top_out(reset_ft[49]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5219,10 +5335,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__11_chanx_left_out), .chany_bottom_in(sb_1__1__3_chany_top_out), .chany_top_in_0(cby_1__1__5_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[13]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[49]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5252,6 +5372,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__4_chanx_right_out), .chany_bottom_out(cby_1__1__4_chany_bottom_out), .chany_top_out_0(sb_1__1__4_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[14]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[50]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5277,10 +5403,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__12_chanx_left_out), .chany_bottom_in(sb_1__1__4_chany_top_out), .chany_top_in_0(cby_1__1__6_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[14]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[50]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5310,6 +5440,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__5_chanx_right_out), .chany_bottom_out(cby_1__1__5_chany_bottom_out), .chany_top_out_0(sb_1__1__5_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[15]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[51]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5335,10 +5471,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__13_chanx_left_out), .chany_bottom_in(sb_1__1__5_chany_top_out), .chany_top_in_0(cby_1__1__7_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[15]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[51]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5368,6 +5508,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__6_chanx_right_out), .chany_bottom_out(cby_1__1__6_chany_bottom_out), .chany_top_out_0(sb_1__1__6_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5392,12 +5538,12 @@ module fpga_top .chanx_left_in(sb_0__8__0_chanx_right_out), .chanx_right_in_0(cbx_1__8__1_chanx_left_out), .chany_bottom_in(sb_1__1__6_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0:3]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5455,7 +5601,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[88:91]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[20]), + .reset_top_in(reset_ft[47]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -5488,10 +5635,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__14_chanx_left_out), .chany_bottom_in(sb_1__0__1_chany_top_out), .chany_top_in_0(cby_1__1__9_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[19]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[46]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5521,6 +5672,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__7_chanx_right_out), .chany_bottom_out(cby_1__1__8_chany_bottom_out), .chany_top_out_0(sb_1__1__7_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[20]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[47]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5546,10 +5703,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__15_chanx_left_out), .chany_bottom_in(sb_1__1__7_chany_top_out), .chany_top_in_0(cby_1__1__10_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[18]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[45]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5579,6 +5740,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__8_chanx_right_out), .chany_bottom_out(cby_1__1__9_chany_bottom_out), .chany_top_out_0(sb_1__1__8_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[19]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[46]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5604,10 +5771,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__16_chanx_left_out), .chany_bottom_in(sb_1__1__8_chany_top_out), .chany_top_in_0(cby_1__1__11_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[17]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[44]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5637,6 +5808,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__9_chanx_right_out), .chany_bottom_out(cby_1__1__10_chany_bottom_out), .chany_top_out_0(sb_1__1__9_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[18]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[45]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5662,10 +5839,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__17_chanx_left_out), .chany_bottom_in(sb_1__1__9_chany_top_out), .chany_top_in_0(cby_1__1__12_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[16]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[40]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5695,6 +5876,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__10_chanx_right_out), .chany_bottom_out(cby_1__1__11_chany_bottom_out), .chany_top_out_0(sb_1__1__10_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[17]), + .prog_reset_right_out(prog_reset_ft[24]), + .prog_reset_top_out(prog_reset_ft[21]), + .reset_bottom_out(reset_ft[44]), + .reset_left_out(reset_ft[48]), + .reset_top_out(reset_ft[41]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5720,10 +5907,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__18_chanx_left_out), .chany_bottom_in(sb_1__1__10_chany_top_out), .chany_top_in_0(cby_1__1__13_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[21]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[41]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5753,6 +5944,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__11_chanx_right_out), .chany_bottom_out(cby_1__1__12_chany_bottom_out), .chany_top_out_0(sb_1__1__11_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[22]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[42]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5778,10 +5975,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__19_chanx_left_out), .chany_bottom_in(sb_1__1__11_chany_top_out), .chany_top_in_0(cby_1__1__14_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[22]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[42]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5811,6 +6012,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__12_chanx_right_out), .chany_bottom_out(cby_1__1__13_chany_bottom_out), .chany_top_out_0(sb_1__1__12_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[23]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[43]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5836,10 +6043,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__20_chanx_left_out), .chany_bottom_in(sb_1__1__12_chany_top_out), .chany_top_in_0(cby_1__1__15_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[23]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[43]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5869,6 +6080,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__13_chanx_right_out), .chany_bottom_out(cby_1__1__14_chany_bottom_out), .chany_top_out_0(sb_1__1__13_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), @@ -5893,12 +6110,12 @@ module fpga_top .chanx_left_in(sb_1__8__0_chanx_right_out), .chanx_right_in_0(cbx_1__8__2_chanx_left_out), .chany_bottom_in(sb_1__1__13_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[4:7]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), @@ -5956,7 +6173,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[84:87]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[28]), + .reset_top_in(reset_ft[39]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -5989,10 +6207,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__21_chanx_left_out), .chany_bottom_in(sb_1__0__2_chany_top_out), .chany_top_in_0(cby_1__1__17_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[27]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[38]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6022,6 +6244,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__14_chanx_right_out), .chany_bottom_out(cby_1__1__16_chany_bottom_out), .chany_top_out_0(sb_1__1__14_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[28]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[39]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6047,10 +6275,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__22_chanx_left_out), .chany_bottom_in(sb_1__1__14_chany_top_out), .chany_top_in_0(cby_1__1__18_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[26]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[37]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6080,6 +6312,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__15_chanx_right_out), .chany_bottom_out(cby_1__1__17_chany_bottom_out), .chany_top_out_0(sb_1__1__15_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[27]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[38]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6105,10 +6343,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__23_chanx_left_out), .chany_bottom_in(sb_1__1__15_chany_top_out), .chany_top_in_0(cby_1__1__19_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[25]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[36]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6138,6 +6380,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__16_chanx_right_out), .chany_bottom_out(cby_1__1__18_chany_bottom_out), .chany_top_out_0(sb_1__1__16_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[26]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[37]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6163,10 +6411,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__24_chanx_left_out), .chany_bottom_in(sb_1__1__16_chany_top_out), .chany_top_in_0(cby_1__1__20_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[24]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[32]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6196,6 +6448,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__17_chanx_right_out), .chany_bottom_out(cby_1__1__19_chany_bottom_out), .chany_top_out_0(sb_1__1__17_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[25]), + .prog_reset_right_out(prog_reset_ft[32]), + .prog_reset_top_out(prog_reset_ft[29]), + .reset_bottom_out(reset_ft[36]), + .reset_left_out(reset_ft[40]), + .reset_top_out(reset_ft[33]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6221,10 +6479,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__25_chanx_left_out), .chany_bottom_in(sb_1__1__17_chany_top_out), .chany_top_in_0(cby_1__1__21_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[29]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[33]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6254,6 +6516,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__18_chanx_right_out), .chany_bottom_out(cby_1__1__20_chany_bottom_out), .chany_top_out_0(sb_1__1__18_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[30]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[34]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6279,10 +6547,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__26_chanx_left_out), .chany_bottom_in(sb_1__1__18_chany_top_out), .chany_top_in_0(cby_1__1__22_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[30]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[34]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6312,6 +6584,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__19_chanx_right_out), .chany_bottom_out(cby_1__1__21_chany_bottom_out), .chany_top_out_0(sb_1__1__19_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[31]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[35]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6337,10 +6615,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__27_chanx_left_out), .chany_bottom_in(sb_1__1__19_chany_top_out), .chany_top_in_0(cby_1__1__23_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[31]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[35]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6370,6 +6652,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__20_chanx_right_out), .chany_bottom_out(cby_1__1__22_chany_bottom_out), .chany_top_out_0(sb_1__1__20_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6394,12 +6682,12 @@ module fpga_top .chanx_left_in(sb_1__8__1_chanx_right_out), .chanx_right_in_0(cbx_1__8__3_chanx_left_out), .chany_bottom_in(sb_1__1__20_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[8:11]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6457,7 +6745,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[80:83]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[36]), + .reset_top_in(reset_ft[31]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -6490,10 +6779,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__28_chanx_left_out), .chany_bottom_in(sb_1__0__3_chany_top_out), .chany_top_in_0(cby_1__1__25_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[35]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[30]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6523,6 +6816,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__21_chanx_right_out), .chany_bottom_out(cby_1__1__24_chany_bottom_out), .chany_top_out_0(sb_1__1__21_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[36]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[31]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6548,10 +6847,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__29_chanx_left_out), .chany_bottom_in(sb_1__1__21_chany_top_out), .chany_top_in_0(cby_1__1__26_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[34]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[29]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6581,6 +6884,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__22_chanx_right_out), .chany_bottom_out(cby_1__1__25_chany_bottom_out), .chany_top_out_0(sb_1__1__22_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[35]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[30]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6606,10 +6915,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__30_chanx_left_out), .chany_bottom_in(sb_1__1__22_chany_top_out), .chany_top_in_0(cby_1__1__27_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[33]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[28]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6639,6 +6952,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__23_chanx_right_out), .chany_bottom_out(cby_1__1__26_chany_bottom_out), .chany_top_out_0(sb_1__1__23_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[34]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[29]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6664,10 +6983,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__31_chanx_left_out), .chany_bottom_in(sb_1__1__23_chany_top_out), .chany_top_in_0(cby_1__1__28_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[32]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[24]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6697,6 +7020,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__24_chanx_right_out), .chany_bottom_out(cby_1__1__27_chany_bottom_out), .chany_top_out_0(sb_1__1__24_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[33]), + .prog_reset_right_out(prog_reset_ft[40]), + .prog_reset_top_out(prog_reset_ft[37]), + .reset_bottom_out(reset_ft[28]), + .reset_left_out(reset_ft[32]), + .reset_top_out(reset_ft[25]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6722,10 +7051,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__32_chanx_left_out), .chany_bottom_in(sb_1__1__24_chany_top_out), .chany_top_in_0(cby_1__1__29_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[37]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[25]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6755,6 +7088,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__25_chanx_right_out), .chany_bottom_out(cby_1__1__28_chany_bottom_out), .chany_top_out_0(sb_1__1__25_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[38]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[26]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6780,10 +7119,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__33_chanx_left_out), .chany_bottom_in(sb_1__1__25_chany_top_out), .chany_top_in_0(cby_1__1__30_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[38]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[26]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6813,6 +7156,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__26_chanx_right_out), .chany_bottom_out(cby_1__1__29_chany_bottom_out), .chany_top_out_0(sb_1__1__26_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[39]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[27]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6838,10 +7187,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__34_chanx_left_out), .chany_bottom_in(sb_1__1__26_chany_top_out), .chany_top_in_0(cby_1__1__31_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[39]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[27]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6871,6 +7224,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__27_chanx_right_out), .chany_bottom_out(cby_1__1__30_chany_bottom_out), .chany_top_out_0(sb_1__1__27_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), @@ -6895,12 +7254,12 @@ module fpga_top .chanx_left_in(sb_1__8__2_chanx_right_out), .chanx_right_in_0(cbx_1__8__4_chanx_left_out), .chany_bottom_in(sb_1__1__27_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[12:15]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), @@ -6958,7 +7317,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[76:79]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[44]), + .reset_top_in(reset_ft[23]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -6991,10 +7351,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__35_chanx_left_out), .chany_bottom_in(sb_1__0__4_chany_top_out), .chany_top_in_0(cby_1__1__33_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[43]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[22]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7024,6 +7388,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__28_chanx_right_out), .chany_bottom_out(cby_1__1__32_chany_bottom_out), .chany_top_out_0(sb_1__1__28_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[44]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[23]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7049,10 +7419,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__36_chanx_left_out), .chany_bottom_in(sb_1__1__28_chany_top_out), .chany_top_in_0(cby_1__1__34_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[42]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[21]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7082,6 +7456,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__29_chanx_right_out), .chany_bottom_out(cby_1__1__33_chany_bottom_out), .chany_top_out_0(sb_1__1__29_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[43]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[22]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7107,10 +7487,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__37_chanx_left_out), .chany_bottom_in(sb_1__1__29_chany_top_out), .chany_top_in_0(cby_1__1__35_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[41]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[20]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7140,6 +7524,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__30_chanx_right_out), .chany_bottom_out(cby_1__1__34_chany_bottom_out), .chany_top_out_0(sb_1__1__30_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[42]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[21]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7165,10 +7555,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__38_chanx_left_out), .chany_bottom_in(sb_1__1__30_chany_top_out), .chany_top_in_0(cby_1__1__36_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[40]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[16]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7198,6 +7592,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__31_chanx_right_out), .chany_bottom_out(cby_1__1__35_chany_bottom_out), .chany_top_out_0(sb_1__1__31_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[41]), + .prog_reset_right_out(prog_reset_ft[48]), + .prog_reset_top_out(prog_reset_ft[45]), + .reset_bottom_out(reset_ft[20]), + .reset_left_out(reset_ft[24]), + .reset_top_out(reset_ft[17]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7223,10 +7623,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__39_chanx_left_out), .chany_bottom_in(sb_1__1__31_chany_top_out), .chany_top_in_0(cby_1__1__37_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[45]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[17]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7256,6 +7660,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__32_chanx_right_out), .chany_bottom_out(cby_1__1__36_chany_bottom_out), .chany_top_out_0(sb_1__1__32_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[46]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[18]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7281,10 +7691,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__40_chanx_left_out), .chany_bottom_in(sb_1__1__32_chany_top_out), .chany_top_in_0(cby_1__1__38_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[46]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[18]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7314,6 +7728,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__33_chanx_right_out), .chany_bottom_out(cby_1__1__37_chany_bottom_out), .chany_top_out_0(sb_1__1__33_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[47]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[19]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7339,10 +7759,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__41_chanx_left_out), .chany_bottom_in(sb_1__1__33_chany_top_out), .chany_top_in_0(cby_1__1__39_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[47]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[19]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7372,6 +7796,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__34_chanx_right_out), .chany_bottom_out(cby_1__1__38_chany_bottom_out), .chany_top_out_0(sb_1__1__34_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7396,12 +7826,12 @@ module fpga_top .chanx_left_in(sb_1__8__3_chanx_right_out), .chanx_right_in_0(cbx_1__8__5_chanx_left_out), .chany_bottom_in(sb_1__1__34_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[16:19]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7459,7 +7889,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[72:75]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[52]), + .reset_top_in(reset_ft[15]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -7492,10 +7923,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__42_chanx_left_out), .chany_bottom_in(sb_1__0__5_chany_top_out), .chany_top_in_0(cby_1__1__41_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[51]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[14]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7525,6 +7960,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__35_chanx_right_out), .chany_bottom_out(cby_1__1__40_chany_bottom_out), .chany_top_out_0(sb_1__1__35_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[52]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[15]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7550,10 +7991,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__43_chanx_left_out), .chany_bottom_in(sb_1__1__35_chany_top_out), .chany_top_in_0(cby_1__1__42_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[50]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[13]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7583,6 +8028,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__36_chanx_right_out), .chany_bottom_out(cby_1__1__41_chany_bottom_out), .chany_top_out_0(sb_1__1__36_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[51]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[14]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7608,10 +8059,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__44_chanx_left_out), .chany_bottom_in(sb_1__1__36_chany_top_out), .chany_top_in_0(cby_1__1__43_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[49]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[12]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7641,6 +8096,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__37_chanx_right_out), .chany_bottom_out(cby_1__1__42_chany_bottom_out), .chany_top_out_0(sb_1__1__37_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[50]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[13]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7666,10 +8127,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__45_chanx_left_out), .chany_bottom_in(sb_1__1__37_chany_top_out), .chany_top_in_0(cby_1__1__44_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[48]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[8]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7699,6 +8164,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__38_chanx_right_out), .chany_bottom_out(cby_1__1__43_chany_bottom_out), .chany_top_out_0(sb_1__1__38_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[49]), + .prog_reset_right_out(prog_reset_ft[56]), + .prog_reset_top_out(prog_reset_ft[53]), + .reset_bottom_out(reset_ft[12]), + .reset_left_out(reset_ft[16]), + .reset_top_out(reset_ft[9]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7724,10 +8195,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__46_chanx_left_out), .chany_bottom_in(sb_1__1__38_chany_top_out), .chany_top_in_0(cby_1__1__45_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[53]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[9]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7757,6 +8232,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__39_chanx_right_out), .chany_bottom_out(cby_1__1__44_chany_bottom_out), .chany_top_out_0(sb_1__1__39_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[54]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[10]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7782,10 +8263,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__47_chanx_left_out), .chany_bottom_in(sb_1__1__39_chany_top_out), .chany_top_in_0(cby_1__1__46_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[54]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[10]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7815,6 +8300,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__40_chanx_right_out), .chany_bottom_out(cby_1__1__45_chany_bottom_out), .chany_top_out_0(sb_1__1__40_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[55]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[11]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7840,10 +8331,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__48_chanx_left_out), .chany_bottom_in(sb_1__1__40_chany_top_out), .chany_top_in_0(cby_1__1__47_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[55]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[11]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7873,6 +8368,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__41_chanx_right_out), .chany_bottom_out(cby_1__1__46_chany_bottom_out), .chany_top_out_0(sb_1__1__41_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), @@ -7897,12 +8398,12 @@ module fpga_top .chanx_left_in(sb_1__8__4_chanx_right_out), .chanx_right_in_0(cbx_1__8__6_chanx_left_out), .chany_bottom_in(sb_1__1__41_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[20:23]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), @@ -7960,7 +8461,8 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[68:71]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_top_in(prog_reset_ft[60]), + .reset_top_in(reset_ft[7]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -7993,10 +8495,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__49_chanx_left_out), .chany_bottom_in(sb_1__0__6_chany_top_out), .chany_top_in_0(cby_1__1__49_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[59]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[6]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8026,6 +8532,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__42_chanx_right_out), .chany_bottom_out(cby_1__1__48_chany_bottom_out), .chany_top_out_0(sb_1__1__42_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[60]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[7]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8051,10 +8563,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__50_chanx_left_out), .chany_bottom_in(sb_1__1__42_chany_top_out), .chany_top_in_0(cby_1__1__50_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[58]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[5]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8084,6 +8600,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__43_chanx_right_out), .chany_bottom_out(cby_1__1__49_chany_bottom_out), .chany_top_out_0(sb_1__1__43_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[59]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[6]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8109,10 +8631,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__51_chanx_left_out), .chany_bottom_in(sb_1__1__43_chany_top_out), .chany_top_in_0(cby_1__1__51_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(), + .prog_reset_top_in(prog_reset_ft[57]), + .reset_bottom_in(), + .reset_right_in(), + .reset_top_in(reset_ft[4]), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8142,6 +8668,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__44_chanx_right_out), .chany_bottom_out(cby_1__1__50_chany_bottom_out), .chany_top_out_0(sb_1__1__44_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[58]), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(reset_ft[5]), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8167,10 +8699,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__52_chanx_left_out), .chany_bottom_in(sb_1__1__44_chany_top_out), .chany_top_in_0(cby_1__1__52_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(), + .prog_reset_left_in(prog_reset_ft[56]), + .prog_reset_top_in(), + .reset_bottom_in(), + .reset_right_in(reset_ft[0]), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8200,6 +8736,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__45_chanx_right_out), .chany_bottom_out(cby_1__1__51_chany_bottom_out), .chany_top_out_0(sb_1__1__45_chany_top_out), + .prog_reset_bottom_out(prog_reset_ft[57]), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[61]), + .reset_bottom_out(reset_ft[4]), + .reset_left_out(reset_ft[8]), + .reset_top_out(reset_ft[1]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8225,10 +8767,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__53_chanx_left_out), .chany_bottom_in(sb_1__1__45_chany_top_out), .chany_top_in_0(cby_1__1__53_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[61]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[1]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8258,6 +8804,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__46_chanx_right_out), .chany_bottom_out(cby_1__1__52_chany_bottom_out), .chany_top_out_0(sb_1__1__46_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[62]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[2]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8283,10 +8835,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__54_chanx_left_out), .chany_bottom_in(sb_1__1__46_chany_top_out), .chany_top_in_0(cby_1__1__54_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[62]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[2]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8316,6 +8872,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__47_chanx_right_out), .chany_bottom_out(cby_1__1__53_chany_bottom_out), .chany_top_out_0(sb_1__1__47_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(prog_reset_ft[63]), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(reset_ft[3]), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8341,10 +8903,14 @@ module fpga_top .chanx_right_in_0(cbx_1__1__55_chanx_left_out), .chany_bottom_in(sb_1__1__47_chany_top_out), .chany_top_in_0(cby_1__1__55_chany_bottom_out), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), + .clk0(clk), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset_bottom_in(prog_reset_ft[63]), + .prog_reset_left_in(), + .prog_reset_top_in(), + .reset_bottom_in(reset_ft[3]), + .reset_right_in(), + .reset_top_in(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8374,6 +8940,12 @@ module fpga_top .chanx_right_out_0(sb_1__1__48_chanx_right_out), .chany_bottom_out(cby_1__1__54_chany_bottom_out), .chany_top_out_0(sb_1__1__48_chany_top_out), + .prog_reset_bottom_out(), + .prog_reset_right_out(), + .prog_reset_top_out(), + .reset_bottom_out(), + .reset_left_out(), + .reset_top_out(), .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8398,12 +8970,12 @@ module fpga_top .chanx_left_in(sb_1__8__5_chanx_right_out), .chanx_right_in_0(cbx_1__8__7_chanx_left_out), .chany_bottom_in(sb_1__1__48_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[24:27]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), @@ -8460,7 +9032,7 @@ module fpga_top .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[64:67]), .isol_n(isol_n), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), @@ -8492,12 +9064,12 @@ module fpga_top .chanx_left_in(sb_1__1__42_chanx_right_out), .chany_bottom_in(sb_8__0__0_chany_top_out), .chany_top_in_0(cby_8__1__1_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[60:63]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8554,12 +9126,12 @@ module fpga_top .chanx_left_in(sb_1__1__43_chanx_right_out), .chany_bottom_in(sb_8__1__0_chany_top_out), .chany_top_in_0(cby_8__1__2_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[56:59]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8616,12 +9188,12 @@ module fpga_top .chanx_left_in(sb_1__1__44_chanx_right_out), .chany_bottom_in(sb_8__1__1_chany_top_out), .chany_top_in_0(cby_8__1__3_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[52:55]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8678,12 +9250,12 @@ module fpga_top .chanx_left_in(sb_1__1__45_chanx_right_out), .chany_bottom_in(sb_8__1__2_chany_top_out), .chany_top_in_0(cby_8__1__4_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[48:51]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8740,12 +9312,12 @@ module fpga_top .chanx_left_in(sb_1__1__46_chanx_right_out), .chany_bottom_in(sb_8__1__3_chany_top_out), .chany_top_in_0(cby_8__1__5_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[44:47]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8802,12 +9374,12 @@ module fpga_top .chanx_left_in(sb_1__1__47_chanx_right_out), .chany_bottom_in(sb_8__1__4_chany_top_out), .chany_top_in_0(cby_8__1__6_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[40:43]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8864,12 +9436,12 @@ module fpga_top .chanx_left_in(sb_1__1__48_chanx_right_out), .chany_bottom_in(sb_8__1__5_chany_top_out), .chany_top_in_0(cby_8__1__7_chany_bottom_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[36:39]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), @@ -8924,13 +9496,13 @@ module fpga_top .ccff_head_1(grid_io_right_right_1_ccff_tail), .chanx_left_in(sb_1__8__6_chanx_right_out), .chany_bottom_in(sb_8__1__6_chany_top_out), + .clk0(clk), .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[28:31]), .gfpga_pad_io_soc_in_0(gfpga_pad_io_soc_in[32:35]), .isol_n(isol_n), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .left_width_0_height_0_subtile_0__pin_reset_0_(reset), .prog_clk(prog_clk), - .prog_reset(prog_reset), + .prog_reset(), + .reset(), .scan_enable(scan_enable), .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v index f6c393b..ea6f317 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v @@ -3,10 +3,10 @@ module grid_clb ( ccff_head, - left_width_0_height_0_subtile_0__pin_clk_0_, - left_width_0_height_0_subtile_0__pin_reset_0_, + clk0, prog_clk, prog_reset, + reset, right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_, right_width_0_height_0_subtile_0__pin_I4i_0_, @@ -66,10 +66,10 @@ module grid_clb ); input ccff_head; - input left_width_0_height_0_subtile_0__pin_clk_0_; - input left_width_0_height_0_subtile_0__pin_reset_0_; + input clk0; input prog_clk; input prog_reset; + input reset; input right_width_0_height_0_subtile_0__pin_I4_0_; input right_width_0_height_0_subtile_0__pin_I4_1_; input right_width_0_height_0_subtile_0__pin_I4i_0_; @@ -132,10 +132,10 @@ module grid_clb wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; wire ccff_head; wire ccff_tail; - wire left_width_0_height_0_subtile_0__pin_clk_0_; - wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire clk0; wire prog_clk; wire prog_reset; + wire reset; wire right_width_0_height_0_subtile_0__pin_I4_0_; wire right_width_0_height_0_subtile_0__pin_I4_1_; wire right_width_0_height_0_subtile_0__pin_I4i_0_; @@ -209,9 +209,9 @@ module grid_clb .clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}), .clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}), .clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_), - .clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_), + .clb_clk(clk0), .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_), - .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_), + .clb_reset(reset), .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_), .prog_clk(prog_clk), .prog_reset(prog_reset), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v index 9521428..5cc951a 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v @@ -6,7 +6,8 @@ module bottom_left_tile chanx_right_in, chany_top_in, prog_clk, - prog_reset, + prog_reset_top_in, + reset_top_in, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, @@ -24,7 +25,8 @@ module bottom_left_tile input [29:0]chanx_right_in; input [29:0]chany_top_in; input prog_clk; - input prog_reset; + input prog_reset_top_in; + input reset_top_in; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; @@ -45,6 +47,8 @@ module bottom_left_tile wire [29:0]chany_top_out; wire prog_clk; wire prog_reset; + wire prog_reset_top_in; + wire reset_top_in; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; @@ -54,6 +58,7 @@ module bottom_left_tile wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +assign prog_reset = prog_reset_top_in; sb_0__0_ sb_0__0_ ( .ccff_head(ccff_head), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v index 58e056f..dc5f6e2 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v @@ -10,7 +10,8 @@ module bottom_tile gfpga_pad_io_soc_in, isol_n, prog_clk, - prog_reset, + prog_reset_top_in, + reset_top_in, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, @@ -44,7 +45,8 @@ module bottom_tile input [3:0]gfpga_pad_io_soc_in; input isol_n; input prog_clk; - input prog_reset; + input prog_reset_top_in; + input reset_top_in; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; @@ -88,6 +90,8 @@ module bottom_tile wire isol_n; wire prog_clk; wire prog_reset; + wire prog_reset_top_in; + wire reset_top_in; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; @@ -105,6 +109,7 @@ module bottom_tile wire top_width_0_height_0_subtile_2__pin_inpad_0_; wire top_width_0_height_0_subtile_3__pin_inpad_0_; +assign prog_reset = prog_reset_top_in; cbx_1__0_ cbx_1__0_ ( .ccff_head(ccff_head), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v index 8564646..d1238db 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v @@ -10,7 +10,12 @@ module left_tile gfpga_pad_io_soc_in, isol_n, prog_clk, - prog_reset, + prog_reset_bottom_in, + prog_reset_left_in, + prog_reset_top_in, + reset_bottom_in, + reset_right_in, + reset_top_in, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, @@ -30,6 +35,11 @@ module left_tile chany_top_out_0, gfpga_pad_io_soc_dir, gfpga_pad_io_soc_out, + prog_reset_bottom_out, + prog_reset_right_out, + prog_reset_top_out, + reset_bottom_out, + reset_top_out, right_width_0_height_0_subtile_0__pin_inpad_0_, right_width_0_height_0_subtile_1__pin_inpad_0_, right_width_0_height_0_subtile_2__pin_inpad_0_, @@ -44,7 +54,12 @@ module left_tile input [3:0]gfpga_pad_io_soc_in; input isol_n; input prog_clk; - input prog_reset; + input prog_reset_bottom_in; + input prog_reset_left_in; + input prog_reset_top_in; + input reset_bottom_in; + input reset_right_in; + input reset_top_in; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -64,6 +79,11 @@ module left_tile output [29:0]chany_top_out_0; output [3:0]gfpga_pad_io_soc_dir; output [3:0]gfpga_pad_io_soc_out; + output prog_reset_bottom_out; + output prog_reset_right_out; + output prog_reset_top_out; + output reset_bottom_out; + output reset_top_out; output right_width_0_height_0_subtile_0__pin_inpad_0_; output right_width_0_height_0_subtile_1__pin_inpad_0_; output right_width_0_height_0_subtile_2__pin_inpad_0_; @@ -87,6 +107,17 @@ module left_tile wire isol_n; wire prog_clk; wire prog_reset; + wire prog_reset_bottom_in; + wire prog_reset_bottom_out; + wire prog_reset_left_in; + wire prog_reset_right_out; + wire prog_reset_top_in; + wire prog_reset_top_out; + wire reset_bottom_in; + wire reset_bottom_out; + wire reset_right_in; + wire reset_top_in; + wire reset_top_out; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -104,6 +135,16 @@ module left_tile wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +assign prog_reset = prog_reset_bottom_in; +assign prog_reset_top_in = prog_reset_left_in; +assign prog_reset_right_out = prog_reset; +assign prog_reset_top_out = prog_reset_right_out; +assign prog_reset_bottom_in = prog_reset_top_in; +assign prog_reset_bottom_out = prog_reset_top_out; +assign reset_top_out = reset_bottom_in; +assign reset_top_in = reset_right_in; +assign reset_bottom_in = reset_top_in; +assign reset_bottom_out = reset_top_out; cby_0__1_ cby_0__1_ ( .ccff_head_0(ccff_head_0), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v index e2d6009..2eb8f2d 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v @@ -8,12 +8,12 @@ module right_tile chanx_left_in, chany_bottom_in, chany_top_in_0, + clk0, gfpga_pad_io_soc_in, isol_n, - left_width_0_height_0_subtile_0__pin_clk_0_, - left_width_0_height_0_subtile_0__pin_reset_0_, prog_clk, prog_reset, + reset, scan_enable, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, @@ -69,12 +69,12 @@ module right_tile input [29:0]chanx_left_in; input [29:0]chany_bottom_in; input [29:0]chany_top_in_0; + input clk0; input [3:0]gfpga_pad_io_soc_in; input isol_n; - input left_width_0_height_0_subtile_0__pin_clk_0_; - input left_width_0_height_0_subtile_0__pin_reset_0_; input prog_clk; input prog_reset; + input reset; input scan_enable; input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; @@ -160,6 +160,7 @@ module right_tile wire [29:0]chany_top_in_0; wire [29:0]chany_top_out; wire [29:0]chany_top_out_0; + wire clk0; wire [3:0]gfpga_pad_io_soc_dir; wire [3:0]gfpga_pad_io_soc_in; wire [3:0]gfpga_pad_io_soc_out; @@ -180,14 +181,13 @@ module right_tile wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; - wire left_width_0_height_0_subtile_0__pin_clk_0_; wire left_width_0_height_0_subtile_0__pin_inpad_0_; - wire left_width_0_height_0_subtile_0__pin_reset_0_; wire left_width_0_height_0_subtile_1__pin_inpad_0_; wire left_width_0_height_0_subtile_2__pin_inpad_0_; wire left_width_0_height_0_subtile_3__pin_inpad_0_; wire prog_clk; wire prog_reset; + wire reset; wire right_width_0_height_0_subtile_0__pin_O_10_; wire right_width_0_height_0_subtile_0__pin_O_11_; wire right_width_0_height_0_subtile_0__pin_O_12_; @@ -288,10 +288,10 @@ module right_tile grid_clb grid_clb_8__1_ ( .ccff_head(ccff_tail_0_0), - .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), - .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .clk0(clk0), .prog_clk(prog_clk), .prog_reset(prog_reset), + .reset(reset), .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v index feeca0c..3d7dd17 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v @@ -8,10 +8,14 @@ module tile chanx_right_in_0, chany_bottom_in, chany_top_in_0, - left_width_0_height_0_subtile_0__pin_clk_0_, - left_width_0_height_0_subtile_0__pin_reset_0_, + clk0, prog_clk, - prog_reset, + prog_reset_bottom_in, + prog_reset_left_in, + prog_reset_top_in, + reset_bottom_in, + reset_right_in, + reset_top_in, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, @@ -41,6 +45,12 @@ module tile chanx_right_out_0, chany_bottom_out, chany_top_out_0, + prog_reset_bottom_out, + prog_reset_right_out, + prog_reset_top_out, + reset_bottom_out, + reset_left_out, + reset_top_out, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, @@ -65,10 +75,14 @@ module tile input [29:0]chanx_right_in_0; input [29:0]chany_bottom_in; input [29:0]chany_top_in_0; - input left_width_0_height_0_subtile_0__pin_clk_0_; - input left_width_0_height_0_subtile_0__pin_reset_0_; + input clk0; input prog_clk; - input prog_reset; + input prog_reset_bottom_in; + input prog_reset_left_in; + input prog_reset_top_in; + input reset_bottom_in; + input reset_right_in; + input reset_top_in; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -98,6 +112,12 @@ module tile output [29:0]chanx_right_out_0; output [29:0]chany_bottom_out; output [29:0]chany_top_out_0; + output prog_reset_bottom_out; + output prog_reset_right_out; + output prog_reset_top_out; + output reset_bottom_out; + output reset_left_out; + output reset_top_out; output right_width_0_height_0_subtile_0__pin_O_10_; output right_width_0_height_0_subtile_0__pin_O_11_; output right_width_0_height_0_subtile_0__pin_O_12_; @@ -152,6 +172,7 @@ module tile wire [29:0]chany_top_in_0; wire [29:0]chany_top_out; wire [29:0]chany_top_out_0; + wire clk0; wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; @@ -168,10 +189,21 @@ module tile wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; - wire left_width_0_height_0_subtile_0__pin_clk_0_; - wire left_width_0_height_0_subtile_0__pin_reset_0_; wire prog_clk; wire prog_reset; + wire prog_reset_bottom_in; + wire prog_reset_bottom_out; + wire prog_reset_left_in; + wire prog_reset_right_out; + wire prog_reset_top_in; + wire prog_reset_top_out; + wire reset; + wire reset_bottom_in; + wire reset_bottom_out; + wire reset_left_out; + wire reset_right_in; + wire reset_top_in; + wire reset_top_out; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -209,6 +241,18 @@ module tile wire top_width_0_height_0_subtile_0__pin_reg_in_0_; wire top_width_0_height_0_subtile_0__pin_sc_in_0_; +assign prog_reset = prog_reset_bottom_in; +assign prog_reset_top_in = prog_reset_left_in; +assign prog_reset_right_out = prog_reset; +assign prog_reset_top_out = prog_reset_right_out; +assign prog_reset_bottom_in = prog_reset_top_in; +assign prog_reset_bottom_out = prog_reset_top_out; +assign reset = reset_bottom_in; +assign reset_top_out = reset_left_out; +assign reset_left_out = reset; +assign reset_top_in = reset_right_in; +assign reset_bottom_in = reset_top_in; +assign reset_bottom_out = reset_top_out; cbx_1__1_ cbx_1__1_ ( .ccff_head(ccff_tail_2), @@ -266,10 +310,10 @@ module tile grid_clb grid_clb_1__1_ ( .ccff_head(ccff_tail_1), - .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), - .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .clk0(clk0), .prog_clk(prog_clk), .prog_reset(prog_reset), + .reset(reset), .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v index c8d1924..4c521a6 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v @@ -6,13 +6,13 @@ module top_right_tile ccff_head_1, chanx_left_in, chany_bottom_in, + clk0, gfpga_pad_io_soc_in, gfpga_pad_io_soc_in_0, isol_n, - left_width_0_height_0_subtile_0__pin_clk_0_, - left_width_0_height_0_subtile_0__pin_reset_0_, prog_clk, prog_reset, + reset, scan_enable, top_width_0_height_0_subtile_0__pin_cin_0_, top_width_0_height_0_subtile_0__pin_reg_in_0_, @@ -58,13 +58,13 @@ module top_right_tile input ccff_head_1; input [29:0]chanx_left_in; input [29:0]chany_bottom_in; + input clk0; input [3:0]gfpga_pad_io_soc_in; input [3:0]gfpga_pad_io_soc_in_0; input isol_n; - input left_width_0_height_0_subtile_0__pin_clk_0_; - input left_width_0_height_0_subtile_0__pin_reset_0_; input prog_clk; input prog_reset; + input reset; input scan_enable; input top_width_0_height_0_subtile_0__pin_cin_0_; input top_width_0_height_0_subtile_0__pin_reg_in_0_; @@ -143,6 +143,7 @@ module top_right_tile wire [29:0]chany_bottom_out; wire [29:0]chany_bottom_out_0; wire [29:0]chany_top_out; + wire clk0; wire [3:0]gfpga_pad_io_soc_dir; wire [3:0]gfpga_pad_io_soc_dir_0; wire [3:0]gfpga_pad_io_soc_in; @@ -166,14 +167,13 @@ module top_right_tile wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; - wire left_width_0_height_0_subtile_0__pin_clk_0_; wire left_width_0_height_0_subtile_0__pin_inpad_0_; - wire left_width_0_height_0_subtile_0__pin_reset_0_; wire left_width_0_height_0_subtile_1__pin_inpad_0_; wire left_width_0_height_0_subtile_2__pin_inpad_0_; wire left_width_0_height_0_subtile_3__pin_inpad_0_; wire prog_clk; wire prog_reset; + wire reset; wire right_width_0_height_0_subtile_0__pin_O_10_; wire right_width_0_height_0_subtile_0__pin_O_11_; wire right_width_0_height_0_subtile_0__pin_O_12_; @@ -270,10 +270,10 @@ module top_right_tile grid_clb grid_clb_8__8_ ( .ccff_head(ccff_tail_0_0), - .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), - .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .clk0(clk0), .prog_clk(prog_clk), .prog_reset(prog_reset), + .reset(reset), .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v index f8eddaf..19a8f31 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v @@ -7,12 +7,12 @@ module top_tile chanx_left_in, chanx_right_in_0, chany_bottom_in, + clk0, gfpga_pad_io_soc_in, isol_n, - left_width_0_height_0_subtile_0__pin_clk_0_, - left_width_0_height_0_subtile_0__pin_reset_0_, prog_clk, prog_reset, + reset, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, @@ -66,12 +66,12 @@ module top_tile input [29:0]chanx_left_in; input [29:0]chanx_right_in_0; input [29:0]chany_bottom_in; + input clk0; input [3:0]gfpga_pad_io_soc_in; input isol_n; - input left_width_0_height_0_subtile_0__pin_clk_0_; - input left_width_0_height_0_subtile_0__pin_reset_0_; input prog_clk; input prog_reset; + input reset; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -158,6 +158,7 @@ module top_tile wire [29:0]chany_bottom_out; wire [29:0]chany_bottom_out_0; wire [29:0]chany_top_out; + wire clk0; wire [3:0]gfpga_pad_io_soc_dir; wire [3:0]gfpga_pad_io_soc_in; wire [3:0]gfpga_pad_io_soc_out; @@ -178,10 +179,9 @@ module top_tile wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; - wire left_width_0_height_0_subtile_0__pin_clk_0_; - wire left_width_0_height_0_subtile_0__pin_reset_0_; wire prog_clk; wire prog_reset; + wire reset; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; @@ -280,10 +280,10 @@ module top_tile grid_clb grid_clb_1__8_ ( .ccff_head(ccff_tail_1), - .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), - .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .clk0(clk0), .prog_clk(prog_clk), .prog_reset(prog_reset), + .reset(reset), .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), diff --git a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt new file mode 100644 index 0000000..3d28afd --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/prog_reset_ports.txt @@ -0,0 +1,8 @@ += = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +Module | In | Out +Module | L R T B | L R T B += = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +bottom_left_tile | - - 1 - | - - - - +bottom_tile | - - 7 - | - - - - +left_tile | 1 - 3 3 | - 1 3 4 +tile | 7 - 21 21 | - 6 21 28 \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt index d57c0c7..cbbd04f 100644 --- a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt +++ b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt @@ -2,6 +2,7 @@ Module | In | Out Module | L R T B | L R T B = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -cbx_1__8_ | - - - 7 | - - - - -cby_1__1_ | - 7 28 14 | 6 - 21 28 -cby_8__1_ | - 1 4 3 | 1 - 3 4 \ No newline at end of file +bottom_left_tile | - - 1 - | - - - - +bottom_tile | - - 7 - | - - - - +left_tile | - 1 3 3 | - - 3 4 +tile | - 7 21 21 | 7 - 21 28 \ No newline at end of file