riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into documenation

This commit is contained in:
Grant Brown 2021-04-04 14:30:43 -06:00
parent f5de2c4b63 7ab54bc1e5
commit f5e5372187
59 changed files with 6370 additions and 269 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
.github/workflows/buildDocker.yml vendored Normal file
View File

@ -0,0 +1,50 @@
# ##############################################################################
# TODO: Add verification task after the netlist modification
################################################################################
name: Arch XML Regression
# Run CI on push on each branch
on:
push:
pull_request:
jobs:
generate_netlist:
name: Arch development
runs-on: ubuntu-18.04
container: ghcr.io/lnis-uofu/openfpga-master:latest
strategy:
fail-fast: false
matrix:
config:
- name: "FPGA1212_QLSOFA_HD"
- name: "FPGA1212_SOFA_CHD"
- name: "FPGA1212_SOFA_HD"
steps:
- name: Runner workspace path
run: |
echo "Cleaning up previous run"
rm -rf "${{ github.workspace }}"
mkdir -p "${{ github.workspace }}"
- name: Checkout OpenFPGA-ArcticPro3 repo
uses: actions/checkout@v2
- name: Detect changes
uses: technote-space/get-diff-action@v4
with:
PATTERNS: |
${{ matrix.config.name }}_PNR/*_task/**
- name: Running benchmark
shell: bash
if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') }}
run: |
${PYTHON_EXEC} -m pip install -r requirements.txt
cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
cd ${{ matrix.config.name }}_PNR && make clean runOpenFPGA
- name: Upload artifact
uses: actions/upload-artifact@v2
if: ${{ failure() }}
with:
name: failed_${{matrix.config.name}}_regression_log
retention-days: 1
path: "${{ matrix.config.name }}_PNR/*_task/latest/*.log"

8
.github/workflows/perform_precheck.sh vendored
View File

@ -8,6 +8,13 @@ cd ./${DEST_DIR}
echo "[Info] Running in directory ${PWD}" echo "[Info] Running in directory ${PWD}"
cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/ cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
status=$?
[ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
fi
fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
make uncompress make uncompress
echo "[Info] All files are uncompressed" echo "[Info] All files are uncompressed"
@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
/usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt /usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
echo "[Info] Create compare_caravel.txt" echo "[Info] Create compare_caravel.txt"
fi fi
echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1

1
.gitignore vendored
View File

@ -11,3 +11,4 @@
**/SRC**/*_tb.v **/SRC**/*_tb.v
**/SDC/**/*.sdc **/SDC/**/*.sdc
!**/SDC/**/disable_configure_ports.sdc !**/SDC/**/disable_configure_ports.sdc
*/runOpenFPGA

26
ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.61e-9
L2_SB_MUX_DELAY: 1.61e-9
L4_SB_MUX_DELAY: 1.61e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9

26
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 0.81e-9
L2_SB_MUX_DELAY: 0.81e-9
L4_SB_MUX_DELAY: 0.81e-9
CB_MUX_DELAY: 0.57e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
LUT4_DELAY: 1.20e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
REGIN_TO_FF0_DELAY: 0.15e-9
FF0_TO_FF1_DELAY: 0.16e-9

26
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

190
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,5 +1,5 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture: SOFA HD
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
@ -11,6 +11,8 @@
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel - 100 routing tracks per channel
- Timing is loaded through an external yml file, so that we can model multiple corners
Authors: Xifan Tang Authors: Xifan Tang
--> -->
<architecture> <architecture>
@ -186,21 +188,6 @@
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -214,41 +201,32 @@
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- Give uniform delays for all the MUXes driving different length of wires
book area formula. This means the mux transistors are about 5x minimum drive strength. TODO: Can be more accurate once the report timing strategies are elaborated
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large -->
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- The wire delay is around 0.1ns in post PnR netlist.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems Create a pair of RC value so that R * C = 0.1ns
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> This is o.k. because other RC values are all zero
-->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -277,18 +255,17 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as The Embedded I/O timing is 0.11ns
the delays to and from registers in the I/O (and generally I/Os are registered FIXME: the timing may include the GPIO timing!!!
today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
@ -296,7 +273,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -306,7 +283,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -386,9 +363,9 @@
<input name="DI" num_pins="1"/> <input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -398,22 +375,22 @@
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/> <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -443,18 +420,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -462,20 +431,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
<!-- Consider the delay of the MUX between LUT3 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -505,20 +476,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
@ -526,20 +488,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -561,15 +525,27 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/> <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${REGIN_TO_FF0_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/> <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/> <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/> <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -591,52 +567,36 @@
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]"> <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]"> <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]"> <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]"> <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]"> <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]"> <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]"> <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]"> <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]"> <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]"> <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]"> <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]"> <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]"> <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]"> <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]"> <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]"> <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -650,7 +610,7 @@
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/--> <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -662,7 +622,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>

169
ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,5 +1,5 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture for QLSOFA_HD.
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
@ -204,21 +204,6 @@
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -232,41 +217,25 @@
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
book area formula. This means the mux transistors are about 5x minimum drive strength. <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -296,10 +265,10 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -315,7 +284,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -325,7 +294,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -430,10 +399,10 @@
<input name="reset" num_pins="1"/> <input name="reset" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -446,22 +415,22 @@
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/> <complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -494,18 +463,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -513,8 +474,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@ -525,8 +486,8 @@
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -556,20 +517,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
@ -577,20 +529,21 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -612,15 +565,23 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/> <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/> <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/> <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/> <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -642,52 +603,36 @@
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]"> <direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]"> <direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]"> <direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]"> <direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]"> <direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]"> <direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]"> <direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]"> <direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]"> <direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]"> <direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]"> <direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]"> <direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]"> <direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]"> <direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]"> <direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]"> <direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -703,7 +648,7 @@
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/--> <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -715,7 +660,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>
@ -724,7 +669,7 @@
<!-- Carry chain links --> <!-- Carry chain links -->
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin"> <direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/> <delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct> </direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout"> <direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
</direct> </direct>

6
DOC/requirements.txt
View File

@ -9,6 +9,12 @@
sphinxcontrib-bibtex<2.0.0 sphinxcontrib-bibtex<2.0.0
sphinxcontrib-tikz sphinxcontrib-tikz
# Package required to embed youtube video
sphinxcontrib-yt
# Package required to convert SVG for latex building
sphinxcontrib-svg2pdfconverter
#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1 #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
#See: #See:
# * https://github.com/sphinx-doc/sphinx/issues/3951 # * https://github.com/sphinx-doc/sphinx/issues/3951

402
DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg Normal file
View File

@ -0,0 +1,402 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<defs>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 7 3 6 5 5 9 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="-1088.8662" x-height="438.96484" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-style="italic" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldItalicMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="13" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="12" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
<g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
<title>schematic_timing</title>
<g id="schematic_timing_图层_1">
<title>图层 1</title>
<g id="Graphic_195">
<rect x="161.78103" y="206.7161" width="392.278" height="213.72704" fill="#ffffc0"/>
<path d="M 554.05904 206.7161 L 161.78103 206.7161 L 161.78103 420.44315 L 554.05904 420.44315 Z" stroke="gray" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="4.0,4.0" stroke-width="1"/>
</g>
<g id="Line_155">
<line x1="293.573" y1="240.8071" x2="383.18888" y2="240" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_151">
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" fill="#417fff"/>
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
<text transform="translate(239.96644 279.72893)" fill="white">
<tspan font-family="Times New Roman" font-size="15" font-weight="700" fill="white" x="1.5981503" y="13">4-LUT</tspan>
</text>
</g>
<g id="Line_149">
<line x1="161.78103" y1="272.12447" x2="235.21038" y2="272.27678" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_148">
<line x1="160.875" y1="311.19668" x2="234.30435" y2="311.349" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_97">
<text transform="translate(137.33138 337.09514)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in3</tspan>
</text>
</g>
<g id="Graphic_95">
<text transform="translate(138.07532 228.09257)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in0</tspan>
</text>
</g>
<g id="Graphic_94">
<text transform="translate(138.07532 266.6768)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in1</tspan>
</text>
</g>
<g id="Graphic_93">
<text transform="translate(137.33138 305.26102)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in2</tspan>
</text>
</g>
<g id="Graphic_82">
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_81">
<path d="M 525.7159 242.52775 L 537.7182 253.49406 L 537.7182 275.12207 L 525.7159 286.69762 L 525.7159 242.52775" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_80">
<text transform="translate(479.9475 265.51445)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[0]</tspan>
</text>
</g>
<g id="Line_79">
<line x1="399.1131" y1="250.70457" x2="521.9307" y2="251.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_78">
<line x1="500.76346" y1="277.83333" x2="524.768" y2="277.88812" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_77">
<line x1="456.921" y1="277.55904" x2="468.9233" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_71">
<line x1="460.1427" y1="289.01437" x2="468.9233" y2="289.01437" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_67">
<line x1="436.98503" y1="277.33333" x2="456.921" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_66">
<line x1="539.9307" y1="266.00524" x2="551.933" y2="266.00524" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_65">
<text transform="translate(557.09085 256.1682)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[0]</tspan>
</text>
</g>
<g id="Graphic_10">
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" fill="#417fff"/>
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_9">
<text transform="translate(385.04194 228.89688)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_159">
<line x1="161.35288" y1="233.11812" x2="234.78222" y2="233.27043" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_184">
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_183">
<path d="M 526.93593 311.8801 L 538.9382 322.84643 L 538.9382 344.47444 L 526.93593 356.05 L 526.93593 311.8801" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_182">
<text transform="translate(480.40556 334.5111)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[1]</tspan>
</text>
</g>
<g id="Line_181">
<line x1="408.22477" y1="323.66667" x2="526.93593" y2="323.47703" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_180">
<line x1="499.3163" y1="346.9114" x2="525.98805" y2="347.2405" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_179">
<line x1="458.141" y1="346.9114" x2="470.1433" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_173">
<line x1="460.0294" y1="358.36674" x2="470.1433" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_169">
<path d="M 405.65013 327.79804 L 405.72657 359.66667 L 437.5637 359.66667 L 435.5637 347.33333 L 458.141 346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_168">
<line x1="541.1507" y1="335.3576" x2="553.153" y2="335.3576" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_167">
<text transform="translate(557.09085 325.5206)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[1]</tspan>
</text>
</g>
<g id="Graphic_166">
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" fill="black"/>
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_187">
<text transform="translate(296.82473 251.7978)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT4_out</tspan>
</text>
</g>
<g id="Line_190">
<line x1="161.35288" y1="344.3335" x2="234.78222" y2="344.4858" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_191">
<line x1="291.7724" y1="271.4607" x2="382.29696" y2="271" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_192">
<line x1="291.5813" y1="324.50875" x2="338.24768" y2="324.04805" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_193">
<text transform="translate(293.65994 219.54083)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[0]</tspan>
</text>
</g>
<g id="Graphic_194">
<text transform="translate(296.20583 305.9816)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[1]</tspan>
</text>
</g>
<g id="Line_201">
<line x1="485.02947" y1="263.61725" x2="485.36365" y2="207.21018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_202">
<text transform="translate(472.91897 189.14374)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scin</tspan>
</text>
</g>
<g id="Line_203">
<path d="M 485.16157 332.66047 L 484.9886 312.79427 L 514.22684 312.5 L 514.4822 277.86465" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_204">
<path d="M 485.14743 421.1854 L 485.14743 393.83333 L 516.0583 393.78353" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_205">
<text transform="translate(467.3559 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scout</tspan>
</text>
</g>
<g id="Line_206">
<line x1="516.10255" y1="420.5187" x2="515.98077" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_207">
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_208">
<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" fill="black"/>
<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_209">
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_210">
<text transform="translate(405.667 188.64967)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regin</tspan>
</text>
</g>
<g id="Graphic_224">
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" fill="#417fff"/>
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_223">
<text transform="translate(435.8671 255.27693)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_226">
<path d="M 421.91773 206.7161 L 421.90706 266.99222 L 434.01406 266.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_227">
<path d="M 405.67654 250.73817 L 405.66667 292.68104 L 433.12215 292.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_228">
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" fill="black"/>
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_230">
<line x1="338.24768" y1="324.04805" x2="402.55997" y2="324.5252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_231">
<text transform="translate(509.788 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regout</tspan>
</text>
</g>
<g id="Graphic_232">
<text transform="translate(130.62533 378.8501)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="#ff2600" x="0" y="11">CLK</tspan>
</text>
</g>
<g id="Line_233">
<path d="M 161.41582 386 L 460.1427 385.33333 L 460.0294 358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_234">
<line x1="460.1427" y1="289.01437" x2="460.0294" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_235">
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" fill="black"/>
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_236">
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" fill="#ccc"/>
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_237">
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" fill="#ccc"/>
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_238">
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" fill="#417fff"/>
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_68">
<text transform="translate(525.46094 242.0072)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_240">
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" fill="#417fff"/>
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_239">
<text transform="translate(527.274 313.7943)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_242">
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" fill="#417fff"/>
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_241">
<text transform="translate(430.4519 328.96835)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_243">
<path d="M 429.21986 340.20005 L 429.816 341 L 416 341.3335 L 416 312.86334 L 484.9886 312.79427" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_244">
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" fill="black"/>
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_245">
<path d="M 187.85625 206.7161 L 187.33333 287.3643 L 207.34185 287.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_246">
<text transform="translate(178.33572 188.64967)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">cin</tspan>
</text>
</g>
<g id="Graphic_248">
<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" fill="#417fff"/>
<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_247">
<text transform="translate(208.61997 279.72197)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_250">
<text transform="translate(293.65994 325.3254)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT2_out[1]</tspan>
</text>
</g>
<g id="Line_249">
<path d="M 291.90178 353.41635 L 291.573 352.66667 L 309 352.418 L 309 403.85204 L 333.20833 403.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_251">
<path d="M 378.5414 394.57625 L 329.502 394.58103 C 329.502 394.58103 336.8721 409.8881 337.15556 409.60465 C 337.43902 409.3212 373.15556 409.3164 373.15556 409.3164 Z" fill="#417fff"/>
<path d="M 378.5414 394.57625 L 329.502 394.58103 C 329.502 394.58103 336.8721 409.8881 337.15556 409.60465 C 337.43902 409.3212 373.15556 409.3164 373.15556 409.3164 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_253">
<path d="M 291.96284 343.09235 L 292.03425 343.22917 L 363.6755 342.5625 L 363.6755 393.22917 L 362.94316 393.90154" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_252">
<text transform="translate(340.8791 396.26126)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">MUX</tspan>
</text>
</g>
<g id="Graphic_254">
<text transform="translate(225.03494 391.5421)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT2_out[0]</tspan>
</text>
</g>
<g id="Line_255">
<path d="M 188.10834 286.21817 L 187.66667 371.33333 L 345.66667 370.66667 L 345.66667 394.57625 L 344.9268 393.91066" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_256">
<ellipse cx="188.10011" cy="287.80266" rx="2.58243758861827" ry="2.75000439423021" fill="black"/>
<ellipse cx="188.10011" cy="287.80266" rx="2.58243758861827" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_258">
<line x1="355.33333" y1="420.44315" x2="355.25323" y2="409.60854" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_259">
<text transform="translate(341.87445 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">cout</tspan>
</text>
</g>
<g id="Line_260">
<path d="M 451.58767 420.66667 L 451.93827 305.5 L 485.3257 305.33333 L 485.2134 298.51603" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_261">
<text transform="translate(424.8676 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">Reset</tspan>
</text>
</g>
<g id="Line_263">
<path d="M 451.72773 374.65874 L 484.909 374.66667 L 485.0261 367.55924" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_264">
<ellipse cx="452.2119" cy="374.65885" rx="2.58243758861829" ry="2.75000439423018" fill="black"/>
<ellipse cx="452.2119" cy="374.65885" rx="2.58243758861829" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_265">
<text transform="translate(400.6399 229.92156)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
</text>
</g>
<g id="Graphic_266">
<text transform="translate(223.72933 316.22945)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
</text>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 27 KiB

2
DOC/source/datasheet/qlsofa_hd/index.rst
View File

@ -14,3 +14,5 @@ QLSOFA HD
qlsofa_hd_clb_arch qlsofa_hd_clb_arch
qlsofa_hd_circuit_design qlsofa_hd_circuit_design
qlsofa_hd_timing

26
DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst
View File

@ -46,6 +46,32 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
| | | cells. | | | | cells. |
+------+----------+----------------------------------------------+ +------+----------+----------------------------------------------+
.. _qlsofa_hd_fpga_arch_routing_arch:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The routing architecture shares the same principle as the SOFA HD routing architecture (See details in :ref:`sofa_hd_fpga_arch_routing_arch`).
.. note:: Different from SOFA HD, each routing channel consists of 60 routing tracks. See details in :numref:`table_qlsofa_hd_fpga_arch_routing_track_distribution`.
.. _table_qlsofa_hd_fpga_arch_routing_track_distribution:
.. table:: Routing track distribution of QLSOFA HD FPGA
+------------+------------------------------+
| Track type | Number of tracks per channel |
+============+==============================+
| Length-1 | 6 (10%) |
+------------+------------------------------+
| Length-2 | 6 (10%) |
+------------+------------------------------+
| Length-4 | 48 (80%) |
+------------+------------------------------+
| Total | 60 |
+------------+------------------------------+
.. _qlsofa_hd_fpga_arch_scan_chain: .. _qlsofa_hd_fpga_arch_scan_chain:
Scan-chain Scan-chain

100
DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst Normal file
View File

@ -0,0 +1,100 @@
.. _qlsofa_hd_timing:
Timing Annotation
-----------------
.. _qlsofa_hd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
.. _fig_qlsofa_hd_fle_arch_timing:
.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in QLSOFA HD FPGA
Schematic of a logic element used in QLSOFA HD FPGA
.. _table_qlsofa_hd_fle_arch_timing:
.. table:: Path delays of logic element in the QLSOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. _qlsofa_hd_timing_io:
I/O Block
^^^^^^^^^
The path delays of I/O blocks in QLSOFA HD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`.
.. _qlsofa_hd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_qlsofa_hd_routing_arch_timing`.
.. _table_qlsofa_hd_routing_arch_timing:
.. table:: Path delays of routing blocks in the QLSOFA HD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.44 |
+---------------------------+------------------------------+
| A -> C | 1.44 |
+---------------------------+------------------------------+
| A -> D | 1.44 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
+---------------------------+------------------------------+

402
DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg Normal file
View File

@ -0,0 +1,402 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<defs>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 7 3 6 5 5 9 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="-1088.8662" x-height="438.96484" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-style="italic" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldItalicMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="13" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="12" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
<g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
<title>schematic_timing</title>
<g id="schematic_timing_图层_1">
<title>图层 1</title>
<g id="Graphic_195">
<rect x="161.78103" y="206.7161" width="392.278" height="213.72704" fill="#ffffc0"/>
<path d="M 554.05904 206.7161 L 161.78103 206.7161 L 161.78103 420.44315 L 554.05904 420.44315 Z" stroke="gray" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="4.0,4.0" stroke-width="1"/>
</g>
<g id="Line_155">
<line x1="293.573" y1="240.8071" x2="383.18888" y2="240" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_151">
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" fill="#417fff"/>
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
<text transform="translate(239.96644 279.72893)" fill="white">
<tspan font-family="Times New Roman" font-size="15" font-weight="700" fill="white" x="1.5981503" y="13">4-LUT</tspan>
</text>
</g>
<g id="Line_149">
<line x1="161.78103" y1="272.12447" x2="235.21038" y2="272.27678" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_148">
<line x1="160.875" y1="311.19668" x2="234.30435" y2="311.349" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_97">
<text transform="translate(137.33138 337.09514)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in3</tspan>
</text>
</g>
<g id="Graphic_95">
<text transform="translate(138.07532 228.09257)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in0</tspan>
</text>
</g>
<g id="Graphic_94">
<text transform="translate(138.07532 266.6768)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in1</tspan>
</text>
</g>
<g id="Graphic_93">
<text transform="translate(137.33138 305.26102)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in2</tspan>
</text>
</g>
<g id="Graphic_82">
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_81">
<path d="M 525.7159 242.52775 L 537.7182 253.49406 L 537.7182 275.12207 L 525.7159 286.69762 L 525.7159 242.52775" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_80">
<text transform="translate(479.9475 265.51445)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[0]</tspan>
</text>
</g>
<g id="Line_79">
<line x1="399.1131" y1="250.70457" x2="521.9307" y2="251.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_78">
<line x1="500.76346" y1="277.83333" x2="524.768" y2="277.88812" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_77">
<line x1="456.921" y1="277.55904" x2="468.9233" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_71">
<line x1="460.1427" y1="289.01437" x2="468.9233" y2="289.01437" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_67">
<line x1="436.98503" y1="277.33333" x2="456.921" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_66">
<line x1="539.9307" y1="266.00524" x2="551.933" y2="266.00524" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_65">
<text transform="translate(557.09085 256.1682)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[0]</tspan>
</text>
</g>
<g id="Graphic_10">
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" fill="#417fff"/>
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_9">
<text transform="translate(385.04194 228.89688)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_159">
<line x1="161.35288" y1="233.11812" x2="234.78222" y2="233.27043" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_184">
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_183">
<path d="M 526.93593 311.8801 L 538.9382 322.84643 L 538.9382 344.47444 L 526.93593 356.05 L 526.93593 311.8801" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_182">
<text transform="translate(480.40556 334.5111)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[1]</tspan>
</text>
</g>
<g id="Line_181">
<line x1="408.22477" y1="323.66667" x2="526.93593" y2="323.47703" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_180">
<line x1="499.3163" y1="346.9114" x2="525.98805" y2="347.2405" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_179">
<line x1="458.141" y1="346.9114" x2="470.1433" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_173">
<line x1="460.0294" y1="358.36674" x2="470.1433" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_169">
<path d="M 405.65013 327.79804 L 405.72657 359.66667 L 437.5637 359.66667 L 435.5637 347.33333 L 458.141 346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_168">
<line x1="541.1507" y1="335.3576" x2="553.153" y2="335.3576" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_167">
<text transform="translate(557.09085 325.5206)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[1]</tspan>
</text>
</g>
<g id="Graphic_166">
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" fill="black"/>
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_187">
<text transform="translate(296.82473 251.7978)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT4_out</tspan>
</text>
</g>
<g id="Line_190">
<line x1="161.35288" y1="344.3335" x2="234.78222" y2="344.4858" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_191">
<line x1="291.7724" y1="271.4607" x2="382.29696" y2="271" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_192">
<line x1="291.5813" y1="324.50875" x2="338.24768" y2="324.04805" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_193">
<text transform="translate(293.65994 219.54083)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[0]</tspan>
</text>
</g>
<g id="Graphic_194">
<text transform="translate(296.20583 305.9816)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[1]</tspan>
</text>
</g>
<g id="Line_201">
<line x1="485.02947" y1="263.61725" x2="485.36365" y2="207.21018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_202">
<text transform="translate(472.91897 189.14374)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scin</tspan>
</text>
</g>
<g id="Line_203">
<path d="M 485.16157 332.66047 L 484.9886 312.79427 L 514.22684 312.5 L 514.4822 277.86465" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_204">
<path d="M 485.14743 421.1854 L 485.14743 393.83333 L 516.0583 393.78353" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_205">
<text transform="translate(467.3559 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scout</tspan>
</text>
</g>
<g id="Line_206">
<line x1="516.10255" y1="420.5187" x2="515.98077" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_207">
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_208">
<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" fill="black"/>
<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_209">
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_210">
<text transform="translate(405.667 188.64967)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regin</tspan>
</text>
</g>
<g id="Graphic_224">
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" fill="#417fff"/>
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_223">
<text transform="translate(435.8671 255.27693)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_226">
<path d="M 421.91773 206.7161 L 421.90706 266.99222 L 434.01406 266.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_227">
<path d="M 405.67654 250.73817 L 405.66667 292.68104 L 433.12215 292.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_228">
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" fill="black"/>
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_230">
<line x1="338.24768" y1="324.04805" x2="402.55997" y2="324.5252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_231">
<text transform="translate(509.788 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regout</tspan>
</text>
</g>
<g id="Graphic_232">
<text transform="translate(130.62533 378.8501)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="#ff2600" x="0" y="11">CLK</tspan>
</text>
</g>
<g id="Line_233">
<path d="M 161.41582 386 L 460.1427 385.33333 L 460.0294 358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_234">
<line x1="460.1427" y1="289.01437" x2="460.0294" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_235">
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" fill="black"/>
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_236">
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" fill="#ccc"/>
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_237">
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" fill="#ccc"/>
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_238">
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" fill="#417fff"/>
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_68">
<text transform="translate(525.46094 242.0072)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_240">
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" fill="#417fff"/>
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_239">
<text transform="translate(527.274 313.7943)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_242">
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" fill="#417fff"/>
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_241">
<text transform="translate(430.4519 328.96835)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_243">
<path d="M 429.21986 340.20005 L 429.816 341 L 416 341.3335 L 416 312.86334 L 484.9886 312.79427" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_244">
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" fill="black"/>
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_245">
<path d="M 187.85625 206.7161 L 187.33333 287.3643 L 207.34185 287.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_246">
<text transform="translate(178.33572 188.64967)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">cin</tspan>
</text>
</g>
<g id="Graphic_248">
<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" fill="#417fff"/>
<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_247">
<text transform="translate(208.61997 279.72197)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Graphic_250">
<text transform="translate(293.65994 325.3254)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT2_out[1]</tspan>
</text>
</g>
<g id="Line_249">
<path d="M 291.90178 353.41635 L 291.573 352.66667 L 309 352.418 L 309 403.85204 L 333.20833 403.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_251">
<path d="M 378.5414 394.57625 L 329.502 394.58103 C 329.502 394.58103 336.8721 409.8881 337.15556 409.60465 C 337.43902 409.3212 373.15556 409.3164 373.15556 409.3164 Z" fill="#417fff"/>
<path d="M 378.5414 394.57625 L 329.502 394.58103 C 329.502 394.58103 336.8721 409.8881 337.15556 409.60465 C 337.43902 409.3212 373.15556 409.3164 373.15556 409.3164 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_253">
<path d="M 291.96284 343.09235 L 292.03425 343.22917 L 363.6755 342.5625 L 363.6755 393.22917 L 362.94316 393.90154" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_252">
<text transform="translate(340.8791 396.26126)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">MUX</tspan>
</text>
</g>
<g id="Graphic_254">
<text transform="translate(225.03494 391.5421)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT2_out[0]</tspan>
</text>
</g>
<g id="Line_255">
<path d="M 188.10834 286.21817 L 187.66667 371.33333 L 345.66667 370.66667 L 345.66667 394.57625 L 344.9268 393.91066" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_256">
<ellipse cx="188.10011" cy="287.80266" rx="2.58243758861827" ry="2.75000439423021" fill="black"/>
<ellipse cx="188.10011" cy="287.80266" rx="2.58243758861827" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_258">
<line x1="355.33333" y1="420.44315" x2="355.25323" y2="409.60854" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_259">
<text transform="translate(341.87445 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">cout</tspan>
</text>
</g>
<g id="Line_260">
<path d="M 451.58767 420.66667 L 451.93827 305.5 L 485.3257 305.33333 L 485.2134 298.51603" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_261">
<text transform="translate(424.8676 421.8724)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">Reset</tspan>
</text>
</g>
<g id="Line_263">
<path d="M 451.72773 374.65874 L 484.909 374.66667 L 485.0261 367.55924" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_264">
<ellipse cx="452.2119" cy="374.65885" rx="2.58243758861829" ry="2.75000439423018" fill="black"/>
<ellipse cx="452.2119" cy="374.65885" rx="2.58243758861829" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_265">
<text transform="translate(400.6399 229.92156)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
</text>
</g>
<g id="Graphic_266">
<text transform="translate(223.72933 316.22945)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
</text>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 27 KiB

2
DOC/source/datasheet/sofa_chd/index.rst
View File

@ -15,4 +15,6 @@ SOFA CHD
sofa_chd_circuit_design sofa_chd_circuit_design
sofa_chd_timing
custom_cells/index custom_cells/index

101
DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst Normal file
View File

@ -0,0 +1,101 @@
.. _sofa_chd_timing:
Timing Annotation
-----------------
.. _sofa_chd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`.
.. _fig_sofa_chd_fle_arch_timing:
.. figure:: ./figures/sofa_chd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in SOFA CHD FPGA
Schematic of a logic element used in SOFA CHD FPGA
.. _table_sofa_chd_fle_arch_timing:
.. table:: Path delays of logic element in the SOFA CHD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.58 |
+-------------------------+------------------------------+
| in2 -> B | 0.16 |
+-------------------------+------------------------------+
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.91 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.63 |
+-------------------------+------------------------------+
| B -> LUT3_out[1] | 0.34 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.20 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.92 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 0.78 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.52 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.17 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.18 |
+-------------------------+------------------------------+
| A -> out[0] | 0.48 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.48 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.47 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.37 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
.. _sofa_chd_timing_io:
I/O Block
^^^^^^^^^
The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`.
.. _sofa_chd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`.
.. _table_sofa_chd_routing_arch_timing:
.. table:: Path delays of routing blocks in the SOFA CHD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 0.81 |
+---------------------------+------------------------------+
| A -> C | 0.81 |
+---------------------------+------------------------------+
| A -> D | 0.81 |
+---------------------------+------------------------------+
| B -> E | 0.57 |
+---------------------------+------------------------------+

328
DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg Normal file
View File

@ -0,0 +1,328 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" xmlns:dc="http://purl.org/dc/elements/1.1/" version="1.1" viewBox="179.00033 169.875 415.5905 256.87067" width="415.5905" height="256.87067">
<defs>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 7 3 6 5 5 9 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="-1088.8662" x-height="438.96484" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-style="italic" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldItalicMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="13" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="12" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
<font-face font-family="Times New Roman" font-size="11" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
<font-face-name name="TimesNewRomanPS-BoldMT"/>
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-02 20:32:49 +0000</metadata>
<g id="frac_lut4_timing_points" stroke-dasharray="none" fill-opacity="1" stroke-opacity="1" fill="none" stroke="none">
<title>frac_lut4_timing_points</title>
<g id="frac_lut4_timing_points_图层_1">
<title>图层 1</title>
<g id="Graphic_195">
<rect x="208.45749" y="190.125" width="344.69553" height="213.72704" fill="#ffffc0"/>
<path d="M 553.153 190.125 L 208.45749 190.125 L 208.45749 403.85204 L 553.153 403.85204 Z" stroke="gray" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="4.0,4.0" stroke-width="1"/>
</g>
<g id="Line_155">
<line x1="293.573" y1="240.8071" x2="383.18888" y2="240" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_151">
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" fill="#417fff"/>
<rect x="234.96644" y="218.1116" width="56.5337" height="139.87187" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
<text transform="translate(239.96644 279.72893)" fill="white">
<tspan font-family="Times New Roman" font-size="15" font-weight="700" fill="white" x="1.5981503" y="13">4-LUT</tspan>
</text>
</g>
<g id="Line_149">
<line x1="208.86372" y1="272.12447" x2="235.21038" y2="272.27678" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_148">
<line x1="208.53864" y1="311.19668" x2="234.8853" y2="311.349" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_97">
<text transform="translate(185.70638 334.22715)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in3</tspan>
</text>
</g>
<g id="Graphic_95">
<text transform="translate(186.45032 225.22458)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in0</tspan>
</text>
</g>
<g id="Graphic_94">
<text transform="translate(186.45032 263.8088)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in1</tspan>
</text>
</g>
<g id="Graphic_93">
<text transform="translate(185.70638 302.39303)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">in2</tspan>
</text>
</g>
<g id="Graphic_82">
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.2566" y="264.61723" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_81">
<path d="M 525.7159 242.52775 L 537.7182 253.49406 L 537.7182 275.12207 L 525.7159 286.69762 L 525.7159 242.52775" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_80">
<text transform="translate(478.9475 265.51445)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[0]</tspan>
</text>
</g>
<g id="Line_79">
<line x1="399.1131" y1="250.70457" x2="521.9307" y2="251.33333" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_78">
<line x1="500.76346" y1="277.83333" x2="524.768" y2="277.88812" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_77">
<line x1="456.921" y1="277.55904" x2="468.9233" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_71">
<line x1="460.1427" y1="289.01437" x2="468.9233" y2="289.01437" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_67">
<line x1="436.98503" y1="277.33333" x2="456.921" y2="277.55904" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_66">
<line x1="539.9307" y1="266.00524" x2="551.933" y2="266.00524" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_65">
<text transform="translate(557.09085 256.1682)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[0]</tspan>
</text>
</g>
<g id="Graphic_10">
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" fill="#417fff"/>
<path d="M 383.18888 227.40694 L 383.19366 276.4463 C 383.19366 276.4463 398.50074 269.07623 398.2173 268.79276 C 397.9338 268.5093 397.92903 232.79276 397.92903 232.79276 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_9">
<text transform="translate(385.04194 228.89688)" fill="white">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
</text>
</g>
<g id="Line_159">
<line x1="208.7101" y1="233.11812" x2="235.05676" y2="233.27043" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_184">
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" fill="#0679ff"/>
<rect x="470.64405" y="333.66043" width="29.338917" height="32.89894" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_183">
<path d="M 526.93593 311.8801 L 538.9382 322.84643 L 538.9382 344.47444 L 526.93593 356.05 L 526.93593 311.8801" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_182">
<text transform="translate(479.4805 334.86682)" fill="white">
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x="0" y="12">FF</tspan>
<tspan font-family="Times New Roman" font-size="13" font-weight="700" fill="white" x=".3618164" y="27.552246">[1]</tspan>
</text>
</g>
<g id="Line_181">
<line x1="408.22477" y1="323.66667" x2="526.93593" y2="323.47703" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_180">
<line x1="499.3163" y1="346.9114" x2="525.98805" y2="347.2405" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_179">
<line x1="458.141" y1="346.9114" x2="470.1433" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_173">
<line x1="460.0294" y1="358.36674" x2="470.1433" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_169">
<path d="M 405.65013 327.79804 L 405.72657 359.66667 L 437.5637 359.66667 L 435.5637 347.33333 L 458.141 346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_168">
<line x1="541.1507" y1="335.3576" x2="553.153" y2="335.3576" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_167">
<text transform="translate(557.09085 325.5206)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">out[1]</tspan>
</text>
</g>
<g id="Graphic_166">
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" fill="black"/>
<ellipse cx="405.64233" cy="324.54805" rx="2.58243758861832" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_187">
<text transform="translate(296.82473 251.7978)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT4_out</tspan>
</text>
</g>
<g id="Line_190">
<line x1="208.7101" y1="344.3335" x2="235.05676" y2="344.4858" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_191">
<line x1="291.7724" y1="271.4607" x2="382.29696" y2="271" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_192">
<line x1="291.5813" y1="324.50875" x2="338.24768" y2="324.04805" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_193">
<text transform="translate(293.65994 219.54083)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[0]</tspan>
</text>
</g>
<g id="Graphic_194">
<text transform="translate(296.20583 305.9816)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">LUT3_out[1]</tspan>
</text>
</g>
<g id="Line_201">
<line x1="484.9261" y1="263.61723" x2="484.9261" y2="189.37067" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_202">
<text transform="translate(472.42364 171.30423)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scin</tspan>
</text>
</g>
<g id="Line_203">
<path d="M 485.16157 332.66047 L 484.9886 312.79427 L 514.22684 312.5 L 514.4822 277.86465" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_204">
<path d="M 485.14743 403.85204 L 485.14743 383.16667 L 516.0583 383.1704" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_205">
<text transform="translate(467.94894 408.67923)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">scout</tspan>
</text>
</g>
<g id="Line_206">
<line x1="516.10255" y1="403.85204" x2="515.98077" y2="346.9114" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_207">
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_208">
<ellipse cx="516.05846" cy="383.237" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="516.05846" cy="383.237" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_209">
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_210">
<text transform="translate(406.6418 171.6428)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regin</tspan>
</text>
</g>
<g id="Graphic_224">
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" fill="#417fff"/>
<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_223">
<text transform="translate(436.33905 258.34065)" fill="white">
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="0" y="10">M</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="22.467285">U</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="34.93457">X</tspan>
</text>
</g>
<g id="Line_226">
<path d="M 422.78366 189.70924 L 421.90706 266.99222 L 434.01406 266.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_227">
<path d="M 405.67654 250.73817 L 405.66667 292.68104 L 433.12215 292.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_228">
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" fill="black"/>
<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_230">
<line x1="338.24768" y1="324.04805" x2="402.55997" y2="324.5252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_231">
<text transform="translate(510.381 408.67923)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">regout</tspan>
</text>
</g>
<g id="Graphic_232">
<text transform="translate(179.00033 375.9821)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="#ff2600" x="0" y="11">CLK</tspan>
</text>
</g>
<g id="Line_233">
<path d="M 208.86372 382 L 460.0294 382.66667 L 460.0294 358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_234">
<line x1="460.1427" y1="289.01437" x2="460.0294" y2="358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_235">
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" fill="black"/>
<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_236">
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" fill="#ccc"/>
<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_237">
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" fill="#ccc"/>
<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_238">
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" fill="#417fff"/>
<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_68">
<text transform="translate(525.93287 245.0709)" fill="white">
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="0" y="10">M</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="22.467285">U</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="34.93457">X</tspan>
</text>
</g>
<g id="Graphic_240">
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" fill="#417fff"/>
<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_239">
<text transform="translate(527.7459 316.85803)" fill="white">
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="0" y="10">M</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="22.467285">U</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="34.93457">X</tspan>
</text>
</g>
<g id="Graphic_242">
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" fill="#417fff"/>
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_241">
<text transform="translate(430.9238 332.03207)" fill="white">
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="0" y="10">M</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="22.467285">U</tspan>
<tspan font-family="Times New Roman" font-size="11" font-weight="700" fill="white" x="1.2192383" y="34.93457">X</tspan>
</text>
</g>
<g id="Line_243">
<path d="M 429.21986 340.20005 L 429.816 341 L 416 341.3335 L 416 312.86334 L 484.9886 312.79427" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_244">
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" fill="black"/>
<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_245">
<text transform="translate(402.6669 228.3304)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
</text>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 22 KiB

365
DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg Normal file
View File

@ -0,0 +1,365 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="185.21496 416.74 449.44856 223.64" width="449.44856" height="223.64">
<defs>
<font-face font-family="Times" font-size="12" panose-1="0 0 5 0 0 0 0 2 0 0" units-per-em="1000" underline-position="-75.68359" underline-thickness="49.316406" slope="0" x-height="453.6133" cap-height="661.6211" ascent="750" descent="-250" font-weight="400">
<font-face-src>
<font-face-name name="Times-Roman"/>
</font-face-src>
</font-face>
<font-face font-family="Times" font-size="12" panose-1="0 0 5 0 0 0 0 9 0 0" units-per-em="1000" underline-position="-75.68359" underline-thickness="49.316406" slope="-1250" x-height="446.28906" cap-height="652.34375" ascent="750" descent="-250" font-style="italic" font-weight="400">
<font-face-src>
<font-face-name name="Times-Italic"/>
</font-face-src>
</font-face>
<font-face font-family="Times" font-size="10" panose-1="0 0 5 0 0 0 0 9 0 0" units-per-em="1000" underline-position="-75.68359" underline-thickness="49.316406" slope="-1500" x-height="446.28906" cap-height="652.34375" ascent="750" descent="-250" font-style="italic" font-weight="400">
<font-face-src>
<font-face-name name="Times-Italic"/>
</font-face-src>
</font-face>
<marker orient="auto" overflow="visible" markerUnits="strokeWidth" id="FilledArrow_Marker" stroke-linejoin="miter" stroke-miterlimit="10" viewBox="-1 -3 6 6" markerWidth="6" markerHeight="6" color="black">
<g>
<path d="M 4 0 L 0 -1.5 L 0 1.5 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
</g>
</marker>
<marker orient="auto" overflow="visible" markerUnits="strokeWidth" id="FilledArrow_Marker_2" stroke-linejoin="miter" stroke-miterlimit="10" viewBox="-1 -2 5 4" markerWidth="5" markerHeight="4" color="black">
<g>
<path d="M 2.4 0 L 0 -.9 L 0 .9 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
</g>
</marker>
<font-face font-family="Times" font-size="12" panose-1="0 0 8 0 0 0 0 9 0 0" units-per-em="1000" underline-position="-66.40625" underline-thickness="67.87109" slope="-1250" x-height="462.8906" cap-height="668.9453" ascent="750" descent="-250" font-style="italic" font-weight="700">
<font-face-src>
<font-face-name name="Times-BoldItalic"/>
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 00:25:42 +0000</metadata>
<g id="Canvas_1" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
<title>Canvas 1</title>
<g id="Canvas_1_Layer_1">
<title>Layer 1</title>
<g id="Graphic_21">
<rect x="222.12" y="626.38" width="9" height="9" fill="#ff2600"/>
<rect x="222.12" y="626.38" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_22">
<rect x="283.37" y="626.38" width="9" height="9" fill="#3733ff"/>
<rect x="283.37" y="626.38" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_23">
<text transform="translate(235.20105 623.88)" fill="black">
<tspan font-family="Times" font-size="12" font-weight="400" fill="black" x="0" y="11">Input Pin</tspan>
</text>
</g>
<g id="Graphic_24">
<text transform="translate(299.1991 623.88)" fill="black">
<tspan font-family="Times" font-size="12" font-weight="400" fill="black" x="0" y="11">Output Pin</tspan>
</text>
</g>
<g id="Graphic_262">
<path d="M 430.56 626.38 L 457.56 626.38 L 448.56 635.38 L 439.56 635.38 Z" fill="#ff2700"/>
<path d="M 430.56 626.38 L 457.56 626.38 L 448.56 635.38 L 439.56 635.38 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_263">
<path d="M 503.965 626.38 L 530.965 626.38 L 521.965 635.38 L 512.965 635.38 Z" fill="#00be00"/>
<path d="M 503.965 626.38 L 530.965 626.38 L 521.965 635.38 L 512.965 635.38 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_264">
<text transform="translate(458.89886 626.38)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">SB MUX</tspan>
</text>
</g>
<g id="Graphic_265">
<text transform="translate(531.30193 626.38)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">CB MUX</tspan>
</text>
</g>
<g id="Graphic_307">
<text transform="translate(387.3187 624.88)" fill="black">
<tspan font-family="Times" font-size="10" font-style="italic" font-weight="400" fill="black" x="0" y="10">Track</tspan>
</text>
</g>
<g id="Line_308">
<line x1="353.34626" y1="632.13" x2="379.83405" y2="632.13" marker-end="url(#FilledArrow_Marker)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_530">
<rect x="293.87" y="417.24" width="63" height="63" fill="#ccc"/>
<rect x="293.87" y="417.24" width="63" height="63" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
<text transform="translate(298.87 434.74)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="15.496094" y="11">CLB</tspan>
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="11.160156" y="25">[2][1]</tspan>
</text>
</g>
<g id="Graphic_531">
<path d="M 277.2 537.4832 L 277.2 510.4832 L 286.2 519.4832 L 286.2 528.4832 Z" fill="#ff2700"/>
<path d="M 277.2 537.4832 L 277.2 510.4832 L 286.2 519.4832 L 286.2 528.4832 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_532">
<rect x="226.44" y="480.24" width="9" height="9" fill="#3434ff"/>
<rect x="226.44" y="480.24" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_533">
<path d="M 230.83645 489.7399 L 230.12382 524.15 L 268.60004 524.0256" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_541">
<rect x="320.87" y="480.24" width="9" height="9" fill="#ff2600"/>
<rect x="320.87" y="480.24" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_542">
<line x1="325.37017" y1="492.65667" x2="325.37" y2="489.24" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_543">
<rect x="199.44" y="417.24" width="63" height="63" fill="#ccc"/>
<rect x="199.44" y="417.24" width="63" height="63" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
<text transform="translate(204.44 434.74)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="15.496094" y="11">CLB</tspan>
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="11.160156" y="25">[1][1]</tspan>
</text>
</g>
<g id="Graphic_544">
<path d="M 338.87 501.6567 L 311.87 501.6567 L 320.87 492.6567 L 329.87 492.6567 Z" fill="#00be00"/>
<path d="M 338.87 501.6567 L 311.87 501.6567 L 320.87 492.6567 L 329.87 492.6567 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_546">
<line x1="325.04645" y1="520.8585" x2="325.1912" y2="510.2559" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_647">
<line x1="286.7" y1="523.9832" x2="360.9" y2="523.9832" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_650">
<ellipse cx="325.0038" cy="523.9832" rx="2.7500043942302" ry="2.62500419449252" fill="black"/>
<ellipse cx="325.0038" cy="523.9832" rx="2.7500043942302" ry="2.62500419449252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_710">
<path d="M 277.41396 575.9316 L 277.41396 548.9316 L 286.41396 557.9316 L 286.41396 566.9316 Z" fill="#ff2700"/>
<path d="M 277.41396 575.9316 L 277.41396 548.9316 L 286.41396 557.9316 L 286.41396 566.9316 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_709">
<path d="M 230.45428 525.9484 L 230.33779 562.5984 L 268.814 562.47396" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_707">
<line x1="286.91396" y1="562.4336" x2="447.38274" y2="562.4968" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_706">
<ellipse cx="324.71503" cy="562.4485" rx="2.7500043942302" ry="2.62500419449254" fill="black"/>
<ellipse cx="324.71503" cy="562.4485" rx="2.7500043942302" ry="2.62500419449254" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_715">
<rect x="392.48274" y="417.24" width="63" height="63" fill="#ccc"/>
<rect x="392.48274" y="417.24" width="63" height="63" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
<text transform="translate(397.48274 434.74)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="15.496094" y="11">CLB</tspan>
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="11.160156" y="25">[3][1]</tspan>
</text>
</g>
<g id="Graphic_714">
<rect x="419.48274" y="480.24" width="9" height="9" fill="#ff2600"/>
<rect x="419.48274" y="480.24" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_713">
<line x1="423.9829" y1="492.65667" x2="423.98274" y2="489.24" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_712">
<path d="M 437.48274 501.6567 L 410.48274 501.6567 L 419.48274 492.6567 L 428.48274 492.6567 Z" fill="#00be00"/>
<path d="M 437.48274 501.6567 L 410.48274 501.6567 L 419.48274 492.6567 L 428.48274 492.6567 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_711">
<line x1="424.02853" y1="520.8582" x2="424.00805" y2="510.25666" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_720">
<rect x="481.0281" y="417.24" width="63" height="63" fill="#ccc"/>
<rect x="481.0281" y="417.24" width="63" height="63" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
<text transform="translate(486.0281 434.74)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="15.496094" y="11">CLB</tspan>
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="11.160156" y="25">[4][1]</tspan>
</text>
</g>
<g id="Graphic_719">
<rect x="508.0281" y="480.24" width="9" height="9" fill="#ff2600"/>
<rect x="508.0281" y="480.24" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_718">
<line x1="512.5283" y1="492.65667" x2="512.5281" y2="489.24" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_717">
<path d="M 526.0281 501.6567 L 499.0281 501.6567 L 508.0281 492.6567 L 517.0281 492.6567 Z" fill="#00be00"/>
<path d="M 526.0281 501.6567 L 499.0281 501.6567 L 508.0281 492.6567 L 517.0281 492.6567 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_725">
<rect x="569.0216" y="417.24" width="63" height="63" fill="#ccc"/>
<rect x="569.0216" y="417.24" width="63" height="63" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
<text transform="translate(574.0216 434.74)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="15.496094" y="11">CLB</tspan>
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="11.160156" y="25">[5][1]</tspan>
</text>
</g>
<g id="Graphic_724">
<rect x="596.0216" y="480.24" width="9" height="9" fill="#ff2600"/>
<rect x="596.0216" y="480.24" width="9" height="9" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_723">
<line x1="600.5218" y1="492.65667" x2="600.5216" y2="489.24" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_722">
<path d="M 614.0216 501.6567 L 587.0216 501.6567 L 596.0216 492.6567 L 605.0216 492.6567 Z" fill="#00be00"/>
<path d="M 614.0216 501.6567 L 587.0216 501.6567 L 596.0216 492.6567 L 605.0216 492.6567 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_726">
<path d="M 369.5 537.4832 L 369.5 510.4832 L 378.5 519.4832 L 378.5 528.4832 Z" fill="#ff2700"/>
<path d="M 369.5 537.4832 L 369.5 510.4832 L 378.5 519.4832 L 378.5 528.4832 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_727">
<ellipse cx="231.09975" cy="524.14684" rx="2.75000439423019" ry="2.62500419449254" fill="black"/>
<ellipse cx="231.09975" cy="524.14684" rx="2.75000439423019" ry="2.62500419449254" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_730">
<line x1="379" y1="523.9832" x2="449.5035" y2="523.9832" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_729">
<ellipse cx="424.03457" cy="523.9832" rx="2.75000439423017" ry="2.62500419449252" fill="black"/>
<ellipse cx="424.03457" cy="523.9832" rx="2.75000439423017" ry="2.62500419449252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_728">
<path d="M 458.1035 537.4832 L 458.1035 510.4832 L 467.28 519.4832 L 467.28 528.4832 Z" fill="#ff2700"/>
<path d="M 458.1035 537.4832 L 458.1035 510.4832 L 467.28 519.4832 L 467.28 528.4832 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_734">
<line x1="512.5281" y1="520.8582" x2="512.5281" y2="510.2567" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_733">
<line x1="467.78" y1="523.9832" x2="537.7835" y2="523.9832" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_732">
<ellipse cx="512.5281" cy="523.9832" rx="2.75000439423021" ry="2.62500419449252" fill="black"/>
<ellipse cx="512.5281" cy="523.9832" rx="2.75000439423021" ry="2.62500419449252" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_731">
<path d="M 546.3835 537.4832 L 546.3835 510.4832 L 555.56 519.4832 L 555.56 528.4832 Z" fill="#ff2700"/>
<path d="M 546.3835 537.4832 L 546.3835 510.4832 L 555.56 519.4832 L 555.56 528.4832 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_737">
<line x1="600.5216" y1="520.5586" x2="600.5216" y2="510.2567" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Line_736">
<line x1="556.06" y1="523.95245" x2="625.56366" y2="523.5322" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_735">
<ellipse cx="600.5216" cy="523.6836" rx="2.75000439423027" ry="2.62500419449245" fill="black"/>
<ellipse cx="600.5216" cy="523.6836" rx="2.75000439423027" ry="2.62500419449245" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_738">
<line x1="324.7385" y1="559.32355" x2="324.91953" y2="535.2079" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_740">
<ellipse cx="424.05025" cy="562.4876" rx="2.7500043942302" ry="2.62500419449251" fill="black"/>
<ellipse cx="424.05025" cy="562.4876" rx="2.7500043942302" ry="2.62500419449251" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_739">
<line x1="424.049" y1="559.3626" x2="424.03914" y2="535.2082" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_741">
<path d="M 458.1035 575.9316 L 458.1035 548.9316 L 467.28 557.9316 L 467.28 566.9316 Z" fill="#ff2700"/>
<path d="M 458.1035 575.9316 L 458.1035 548.9316 L 467.28 557.9316 L 467.28 566.9316 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_746">
<line x1="467.78" y1="562.4036" x2="623.92175" y2="561.54456" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_745">
<ellipse cx="511.55104" cy="562.1628" rx="2.75000439423024" ry="2.62500419449248" fill="black"/>
<ellipse cx="511.55104" cy="562.1628" rx="2.75000439423024" ry="2.62500419449248" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_744">
<line x1="511.57524" y1="559.0379" x2="511.76365" y2="534.708" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_743">
<ellipse cx="600.1252" cy="561.6755" rx="2.7500043942303" ry="2.62500419449248" fill="black"/>
<ellipse cx="600.1252" cy="561.6755" rx="2.7500043942303" ry="2.62500419449248" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_742">
<line x1="600.1578" y1="558.55064" x2="600.4045" y2="534.908" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_760">
<path d="M 277.81564 614.0958 L 277.81564 587.0958 L 286.81564 596.0958 L 286.81564 605.0958 Z" fill="#ff2700"/>
<path d="M 277.81564 614.0958 L 277.81564 587.0958 L 286.81564 596.0958 L 286.81564 605.0958 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_759">
<path d="M 230.33297 564.72413 L 230.23947 601.2626 L 269.21635 600.76355" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_758">
<text transform="translate(185.21496 593.2043)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">L4 Wire</tspan>
</text>
</g>
<g id="Line_757">
<line x1="287.31564" y1="600.5873" x2="623.9216" y2="600.0138" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_756">
<ellipse cx="325.3902" cy="600.52244" rx="2.75000439423021" ry="2.62500419449248" fill="black"/>
<ellipse cx="325.3902" cy="600.52244" rx="2.75000439423021" ry="2.62500419449248" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_755">
<line x1="325.3895" y1="597.39744" x2="325.3839" y2="573.37236" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_754">
<ellipse cx="424.6161" cy="600.3534" rx="2.75000439423015" ry="2.62500419449251" fill="black"/>
<ellipse cx="424.6161" cy="600.3534" rx="2.75000439423015" ry="2.62500419449251" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_753">
<line x1="424.6002" y1="597.2284" x2="424.47875" y2="573.37234" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_750">
<ellipse cx="512.097" cy="600.2043" rx="2.75000439423021" ry="2.62500419449254" fill="black"/>
<ellipse cx="512.097" cy="600.2043" rx="2.75000439423021" ry="2.62500419449254" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_749">
<line x1="512.10857" y1="597.07935" x2="512.1981" y2="572.8724" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_748">
<ellipse cx="600.84156" cy="600.0531" rx="2.75000439423027" ry="2.62500419449257" fill="black"/>
<ellipse cx="600.84156" cy="600.0531" rx="2.75000439423027" ry="2.62500419449257" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Line_747">
<line x1="600.7832" y1="596.9286" x2="600.3347" y2="572.8986" marker-end="url(#FilledArrow_Marker_2)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
</g>
<g id="Graphic_761">
<text transform="translate(185.21496 555.4876)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">L2 Wire</tspan>
</text>
</g>
<g id="Graphic_762">
<text transform="translate(185.21496 514.8)" fill="black">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">L1 Wire</tspan>
</text>
</g>
<g id="Graphic_772">
<text transform="translate(237.8159 507.96)" fill="#ff2600">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="11">A</tspan>
</text>
</g>
<g id="Graphic_773">
<text transform="translate(329.55024 507.96)" fill="#ff2600">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="11">B</tspan>
</text>
</g>
<g id="Graphic_774">
<ellipse cx="230.34096" cy="561.59914" rx="2.75000439423017" ry="2.62500419449248" fill="black"/>
<ellipse cx="230.34096" cy="561.59914" rx="2.75000439423017" ry="2.62500419449248" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
</g>
<g id="Graphic_775">
<text transform="translate(411.2311 545.4)" fill="#ff2600">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="11">C</tspan>
</text>
</g>
<g id="Graphic_776">
<text transform="translate(587.0216 582.84)" fill="#ff2600">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="11">D</tspan>
</text>
</g>
<g id="Graphic_777">
<text transform="translate(336.9594 478.6567)" fill="#ff2600">
<tspan font-family="Times" font-size="12" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="11">E</tspan>
</text>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 25 KiB

2
DOC/source/datasheet/sofa_hd/index.rst
View File

@ -14,3 +14,5 @@ SOFA HD
sofa_hd_clb_arch sofa_hd_clb_arch
sofa_hd_circuit_design sofa_hd_circuit_design
sofa_hd_timing

41
DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst
View File

@ -59,6 +59,47 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
| | | cells. | | | | cells. |
+------+----------+----------------------------------------------+ +------+----------+----------------------------------------------+
.. _sofa_hd_fpga_arch_routing_arch:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers.
:numref:`fig_sofa_hd_routing_arch` illustrates the detailed organization of the routing architecture.
.. _fig_sofa_hd_routing_arch:
.. figure:: ./figures/sofa_hd_routing_arch.svg
:width: 80%
:alt: Detailed routing architecture
Detailed routing architecture
The routing architecture consists the following type of routing tracks:
- Length-1 wires (``L1 wires``), which hop over 1 logic block (including I/O block)
- Length-2 wires (``L2 wires``), which hop over 2 logic block (including I/O block)
- Length-4 wires (``L4 wires``), which hop over 4 logic block (including I/O block)
Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles.
Each routing channel consists of 40 routing tracks. See details in :numref:`table_sofa_hd_fpga_arch_routing_track_distribution`.
.. _table_sofa_hd_fpga_arch_routing_track_distribution:
.. table:: Routing track distribution of SOFA HD FPGA
+------------+------------------------------+
| Track type | Number of tracks per channel |
+============+==============================+
| Length-1 | 4 (10%) |
+------------+------------------------------+
| Length-2 | 4 (10%) |
+------------+------------------------------+
| Length-4 | 32 (80%) |
+------------+------------------------------+
| Total | 40 |
+------------+------------------------------+
.. _sofa_hd_fpga_arch_scan_chain: .. _sofa_hd_fpga_arch_scan_chain:
Scan-chain Scan-chain

110
DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst Normal file
View File

@ -0,0 +1,110 @@
.. _sofa_hd_timing:
Timing Annotation
-----------------
.. _sofa_hd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
.. _fig_sofa_hd_fle_arch_timing:
.. figure:: ./figures/sofa_hd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in SOFA HD FPGA
Schematic of a logic element used in SOFA HD FPGA
.. _table_sofa_hd_fle_arch_timing:
.. table:: Path delays of logic element in the SOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] | 0.30 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.59 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] | 0.31 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.14 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.86 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 0.58 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.51 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. _sofa_hd_timing_io:
I/O Block
^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`.
.. _table_sofa_hd_io_timing:
.. table:: Path delays of I/O circuit in the SOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| SOC_IN -> FPGA_IN | 0.11 |
+-------------------------+------------------------------+
| FPGA_OUT -> SOC_OUT | 0.11 |
+-------------------------+------------------------------+
.. _sofa_hd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`.
.. _table_sofa_hd_routing_arch_timing:
.. table:: Path delays of routing blocks in the SOFA HD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.61 |
+---------------------------+------------------------------+
| A -> C | 1.61 |
+---------------------------+------------------------------+
| A -> D | 1.61 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
+---------------------------+------------------------------+

BIN
DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 372 KiB

BIN
DOC/source/device/hd_fpga/figures/sofa_chd_layout.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 357 KiB

BIN
DOC/source/device/hd_fpga/figures/sofa_hd_layout.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 374 KiB

39
DOC/source/device/hd_fpga/hd_device_gallery.rst Normal file
View File

@ -0,0 +1,39 @@
.. _hd_fpga_device_gallery:
Chip Gallery
------------
Here lists the images of each HD FPGA chips
SOFA HD
^^^^^^^
SOFA HD is the base design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/sofa_hd_layout.png
:scale: 100%
:alt: Layout view of SOFA HD device in Caravel SoC
Layout view of SOFA HD device in Caravel SoC
QLSOFA HD
^^^^^^^^^
QLSOFA HD is the arithmetic-enhanced design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/qlsofa_hd_layout.png
:scale: 100%
:alt: Layout view of QLSOFA HD device in Caravel SoC
Layout view of QLSOFA HD device in Caravel SoC
SOFA CHD
^^^^^^^^
SOFA CHD is the performance-optimized design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/sofa_chd_layout.png
:scale: 100%
:alt: Layout view of SOFA CHD device in Caravel SoC
Layout view of SOFA CHD device in Caravel SoC

2
DOC/source/device/hd_fpga/index.rst
View File

@ -10,3 +10,5 @@ HD FPGAs
hd_device_comp hd_device_comp
hd_device_dcac hd_device_dcac
hd_device_gallery

1
DOC/source/device/introduction.rst
View File

@ -17,4 +17,3 @@ We aims to empower embedded applications with its low-cost design approach but h
:alt: 24-hour FPGA IP development: from PDK to production-ready layout :alt: 24-hour FPGA IP development: from PDK to production-ready layout
24-hour FPGA IP development: from PDK to production-ready layout 24-hour FPGA IP development: from PDK to production-ready layout

20
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
View File

@ -13,21 +13,27 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
fpga_flow=vpr_blif fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = top bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_formal_verification_top_netlist=

40
FPGA1212_QLSOFA_HD_PNR/Makefile Normal file
View File

@ -0,0 +1,40 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

20
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf
View File

@ -13,21 +13,27 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
fpga_flow=vpr_blif fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = top bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_formal_verification_top_netlist=

40
FPGA1212_SOFA_CHD_PNR/Makefile Normal file
View File

@ -0,0 +1,40 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

20
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf
View File

@ -13,21 +13,27 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
fpga_flow=vpr_blif fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = top bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_formal_verification_top_netlist=

40
FPGA1212_SOFA_HD_PNR/Makefile Normal file
View File

@ -0,0 +1,40 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

3318
LIB/sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib Normal file
View File

File diff suppressed because it is too large Load Diff

59
README.md
View File

@ -4,23 +4,64 @@
## Introduction ## Introduction
SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.
This repository provide the following support for the eFPGA IPs
- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs.
- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details
<p>
<img src="./DOC/source/device/hd_fpga/figures/sofa_hd_layout.png" width="200">
<img src="./DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png" width="200">
<img src="./DOC/source/device/hd_fpga/figures/sofa_chd_layout.png" width="200">
</p>
## Quick Start ## Quick Start
To run the user flow using SOFA repository you need to have OpenFPGA installed.
Please visit https://github.com/lnis-uofu/OpenFPGA#compilation for OpenFPGA installaton.
```bash ```bash
#Clone the repository and go inside it export OPENFPGA_PATH=<path_to_openfpga_root>
git clone https://github.com/LNIS-Projects/skywater-openfpga.git
python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY} # Clone the SOFA repository
git clone https://github.com/lnis-uofu/SOFA.git
# ======== Goto specific design ========
# FPGA1212_SOFA_CHD_PNR
# FPGA1212_QLSOFA_HD_PNR
# FPGA1212_SOFA_HD_PNR
cd FPGA1212_QLSOFA_HD_PNR
# ======== Run example OpenFPGA Task ========
make runOpenFPGA
# ======== To view the results ========
cat FPGA1212_QLSOFA_HD_task/latest/task_result.csv
# ======== To view detailed log ========
cat codeopen FPGA1212_QLSOFA_HD_task/latest/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/**/openfpgashell.log
``` ```
### To bechmark your own design
Copy your verilog file `FPGA1212_QLSOFA_HD_task/micro_benchmark` directory
and modify `FPGA1212_QLSOFA_HD_task/config/task_simulation.conf` file.
Details of different paramters can be found [Configure run_fpga_task](https://openfpga.readthedocs.io/en/latest/manual/openfpga_flow/run_fpga_task/)
```bash
cd FPGA1212_QLSOFA_HD_PNR
vi FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
```
--- ---
* If you have openfpga repository cloned at the same level of this project, you can simple call ## Chip Gallery
```bash
python3 SCRIPT/repo_setup.py
```
Otherwise, you should provide full path using the option _--openfpga\_root\_path_ You can find a chip gallery in the online documentation
## Directory Organization ## Directory Organization

49
SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga Normal file
View File

@ -0,0 +1,49 @@
# This script is designed to generate bitstream
# with a fixed device layout, which can be used for bitstream loaders
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup #--verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
# - Enabled frame view creation to save runtime and memory
# Note that this is turned on when bitstream generation
# is the ONLY purpose of the flow!!!
build_fabric --compress_routing --duplicate_grid_pin --frame_view --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Finish and exit OpenFPGA
exit

53
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf Normal file
View File

@ -0,0 +1,53 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

53
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf Normal file
View File

@ -0,0 +1,53 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

53
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf Normal file
View File

@ -0,0 +1,53 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

96
SNPS_PT/SCRIPT/report_timing_cb.tcl Normal file
View File

@ -0,0 +1,96 @@
#####################################################################
# A template script to report timing for Connection Blocks from post-PnR results
# using Synopsys PrimeTime
#####################################################################
#
##################################
# Define environment variables
#
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths true
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Sweep all the CB design
set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"};
foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
#########################################
# Setup constraints for clocks
#source ${SDC_HOME}/global_ports.sdc
#########################################
# Setup constraints for paths
# Connection block name
set CB_CHAN_NAME "chan*";
set CB_PIN_NAME "*grid_pin*";
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
##################################
# Finish and quit
# Comment it out if you want to debug
exit

136
SNPS_PT/SCRIPT/report_timing_clb.tcl Normal file
View File

@ -0,0 +1,136 @@
#####################################################################
# A template script to report timing for A CLB from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
#
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
# Top-level module name
set DESIGN_NAME "grid_clb";
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
if {${DEVICE_NAME} == "SOFA_HD"} {
set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
} else {
# QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
# Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
set_disable_timing */*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
set_disable_timing */*/*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
#Disable cin/cout paths
set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cin
set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cout
}
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
# LUT4 output timing
set LUT_INPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in"
set LUT4_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out"
# Walk through all the input pin and output pin paths
for {set ipin 0} {$ipin < 4} {incr ipin} {
if {0 == $ipin} {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
} else {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
}
}
# LUT3 output timing
set LUT3_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out"
# Walk through all the input pin and output pin paths
for {set ipin 0} {$ipin < 3} {incr ipin} {
for {set opin 0} {$opin < 2} {incr opin} {
if {0 == $ipin && 0 == $opin} {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
} else {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
}
}
}
# Output selector timing
set FRAC_LOGIC_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]"
set FF_PATH "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff"
set FLE_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out"
report_timing -from ${FF_PATH}_0/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[0] -to ${FLE_OUTPUT_PORT_NAME}[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FF_PATH}_1/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[1] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
# LUT output to FF input timing
report_timing -from ${LUT4_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
# TODO: Carry logic timing
##################################
# Finish and quit
# Comment it out if you want to debug
exit

87
SNPS_PT/SCRIPT/report_timing_io.tcl Normal file
View File

@ -0,0 +1,87 @@
#####################################################################
# A template script to report timing for A CLB from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
# Top-level module name
# May sweep for all the io modules
set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0";
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
# Inpad -> FPGA timing
report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
##################################
# Finish and quit
# Comment it out if you want to debug
exit

94
SNPS_PT/SCRIPT/report_timing_sb.tcl Normal file
View File

@ -0,0 +1,94 @@
#####################################################################
# A template script to report timing for Connection Blocks from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
#set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
if {"SOFA_CHD" == ${DEVICE_NAME}} {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
} else {
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
}
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Sweep all the SB designs
set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"};
foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
if {"SOFA_CHD" == ${DEVICE_NAME}} {
read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
}
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
## Switch block name
set SB_CHAN_NAME "chan*";
set SB_PIN_NAME "*grid_pin*";
set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
##################################
# Finish and quit
# Comment it out if you want to debug
exit

3
SynRepoConfig/sync_files_qlsofa_hd.csv
View File

@ -1,4 +1,5 @@
SrcLoc, DestLoc SrcLoc, DestLoc
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
3 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

3
SynRepoConfig/sync_files_sofa_chd.csv
View File

@ -1,4 +1,5 @@
SrcLoc, DestLoc SrcLoc, DestLoc
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
3 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

2
SynRepoConfig/sync_files_sofa_hd.csv
View File

@ -2,4 +2,4 @@ SrcLoc, DestLoc
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
3 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v