mirror of https://github.com/lnis-uofu/SOFA.git
102 lines
4.4 KiB
ReStructuredText
102 lines
4.4 KiB
ReStructuredText
.. _sofa_chd_timing:
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Timing Annotation
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-----------------
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.. _sofa_chd_timing_clb:
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Configurable Logic Block
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^^^^^^^^^^^^^^^^^^^^^^^^
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The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`.
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.. _fig_sofa_chd_fle_arch_timing:
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.. figure:: ./figures/sofa_chd_fle_arch_timing.svg
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:width: 80%
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:alt: Schematic of a logic element used in SOFA CHD FPGA
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Schematic of a logic element used in SOFA CHD FPGA
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.. _table_sofa_chd_fle_arch_timing:
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.. table:: Path delays of logic element in the SOFA CHD FPGA
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+-------------------------+------------------------------+
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| Path / Delay | TT (unit: ns) |
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+=========================+==============================+
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| in0 -> LUT3_out[0] | 0.86 |
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+-------------------------+------------------------------+
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| in1 -> LUT3_out[0] | 0.58 |
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+-------------------------+------------------------------+
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| in2 -> B | 0.16 |
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+-------------------------+------------------------------+
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| B -> LUT3_out[0] | 0.32 |
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+-------------------------+------------------------------+
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| in0 -> LUT3_out[1] | 0.91 |
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+-------------------------+------------------------------+
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| in1 -> LUT3_out[1] | 0.63 |
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+-------------------------+------------------------------+
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| B -> LUT3_out[1] | 0.34 |
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+-------------------------+------------------------------+
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| in0 -> LUT4_out | 1.20 |
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+-------------------------+------------------------------+
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| in1 -> LUT4_out | 0.92 |
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+-------------------------+------------------------------+
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| in2 -> LUT4_out | 0.78 |
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+-------------------------+------------------------------+
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| in3 -> LUT4_out | 0.52 |
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+-------------------------+------------------------------+
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| LUT3_out[0] -> A | 0.17 |
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+-------------------------+------------------------------+
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| LUT4_out[0] -> A | 0.18 |
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+-------------------------+------------------------------+
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| A -> out[0] | 0.48 |
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+-------------------------+------------------------------+
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| A -> FF[0] | 0.15 |
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+-------------------------+------------------------------+
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| FF[0] -> out[0] | 0.48 |
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+-------------------------+------------------------------+
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| LUT3_out[1] -> out[1] | 0.47 |
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+-------------------------+------------------------------+
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| LUT3_out[1] -> FF[1] | 0.16 |
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+-------------------------+------------------------------+
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| FF[1] -> out[1] | 0.37 |
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+-------------------------+------------------------------+
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| regin -> FF[0] | 0.15 |
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+-------------------------+------------------------------+
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| FF[0] -> FF[1] | 0.16 |
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+-------------------------+------------------------------+
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.. _sofa_chd_timing_io:
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I/O Block
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^^^^^^^^^
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The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`.
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.. _sofa_chd_timing_routing:
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Routing Architecture
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^^^^^^^^^^^^^^^^^^^^
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The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`.
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.. _table_sofa_chd_routing_arch_timing:
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.. table:: Path delays of routing blocks in the SOFA CHD FPGA
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+---------------------------+------------------------------+
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| Path / Delay | TT (unit: ns) |
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+===========================+==============================+
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| A -> B | 0.81 |
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+---------------------------+------------------------------+
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| A -> C | 0.81 |
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+---------------------------+------------------------------+
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| A -> D | 0.81 |
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+---------------------------+------------------------------+
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| B -> E | 0.57 |
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+---------------------------+------------------------------+
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