.. _sofa_chd_timing: Timing Annotation ----------------- .. _sofa_chd_timing_clb: Configurable Logic Block ^^^^^^^^^^^^^^^^^^^^^^^^ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`. .. _fig_sofa_chd_fle_arch_timing: .. figure:: ./figures/sofa_chd_fle_arch_timing.svg :width: 80% :alt: Schematic of a logic element used in SOFA CHD FPGA Schematic of a logic element used in SOFA CHD FPGA .. _table_sofa_chd_fle_arch_timing: .. table:: Path delays of logic element in the SOFA CHD FPGA +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ | in0 -> LUT3_out[0] | 0.86 | +-------------------------+------------------------------+ | in1 -> LUT3_out[0] | 0.58 | +-------------------------+------------------------------+ | in2 -> B | 0.16 | +-------------------------+------------------------------+ | B -> LUT3_out[0] | 0.32 | +-------------------------+------------------------------+ | in0 -> LUT3_out[1] | 0.91 | +-------------------------+------------------------------+ | in1 -> LUT3_out[1] | 0.63 | +-------------------------+------------------------------+ | B -> LUT3_out[1] | 0.34 | +-------------------------+------------------------------+ | in0 -> LUT4_out | 1.20 | +-------------------------+------------------------------+ | in1 -> LUT4_out | 0.92 | +-------------------------+------------------------------+ | in2 -> LUT4_out | 0.78 | +-------------------------+------------------------------+ | in3 -> LUT4_out | 0.52 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.17 | +-------------------------+------------------------------+ | LUT4_out[0] -> A | 0.18 | +-------------------------+------------------------------+ | A -> out[0] | 0.48 | +-------------------------+------------------------------+ | A -> FF[0] | 0.15 | +-------------------------+------------------------------+ | FF[0] -> out[0] | 0.48 | +-------------------------+------------------------------+ | LUT3_out[1] -> out[1] | 0.47 | +-------------------------+------------------------------+ | LUT3_out[1] -> FF[1] | 0.16 | +-------------------------+------------------------------+ | FF[1] -> out[1] | 0.37 | +-------------------------+------------------------------+ | regin -> FF[0] | 0.15 | +-------------------------+------------------------------+ | FF[0] -> FF[1] | 0.16 | +-------------------------+------------------------------+ .. _sofa_chd_timing_io: I/O Block ^^^^^^^^^ The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. .. _sofa_chd_timing_routing: Routing Architecture ^^^^^^^^^^^^^^^^^^^^ The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`. .. _table_sofa_chd_routing_arch_timing: .. table:: Path delays of routing blocks in the SOFA CHD FPGA +---------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +===========================+==============================+ | A -> B | 0.81 | +---------------------------+------------------------------+ | A -> C | 0.81 | +---------------------------+------------------------------+ | A -> D | 0.81 | +---------------------------+------------------------------+ | B -> E | 0.57 | +---------------------------+------------------------------+