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[Testbench] Add testbenches for RTL and Gate-level netlists of Caravel

This commit is contained in:
tangxifan 2020-12-15 16:13:34 -07:00
parent 255b29b59d
commit 80d79a6eb1
3 changed files with 26 additions and 3 deletions
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13
TESTBENCH/common/caravel_fpga_io_test_gl_include_netlists.v Normal file
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//-------------------------------------------
// A file to include all the dependency HDL codes
// required by Caravel gate-level netlists
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// Include caravel gate-level netlists
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_gl_include_netlists.v"
// Include testbench files
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"

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TESTBENCH/common/caravel_fpga_io_test_include_netlists.v (Stored with Git LFS)
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13
TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v Normal file
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//-------------------------------------------
// A file to include all the dependency HDL codes
// required by Caravel gate-level netlists
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// Include caravel gate-level netlists
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_rtl_include_netlists.v"
// Include testbench files
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"