From 80d79a6eb1530a5bcd834f5d0ff7143140d3121a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Dec 2020 16:13:34 -0700 Subject: [PATCH] [Testbench] Add testbenches for RTL and Gate-level netlists of Caravel --- .../caravel_fpga_io_test_gl_include_netlists.v | 13 +++++++++++++ .../common/caravel_fpga_io_test_include_netlists.v | 3 --- .../caravel_fpga_io_test_rtl_include_netlists.v | 13 +++++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 TESTBENCH/common/caravel_fpga_io_test_gl_include_netlists.v delete mode 100644 TESTBENCH/common/caravel_fpga_io_test_include_netlists.v create mode 100644 TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v diff --git a/TESTBENCH/common/caravel_fpga_io_test_gl_include_netlists.v b/TESTBENCH/common/caravel_fpga_io_test_gl_include_netlists.v new file mode 100644 index 0000000..34174ad --- /dev/null +++ b/TESTBENCH/common/caravel_fpga_io_test_gl_include_netlists.v @@ -0,0 +1,13 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Include caravel gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_gl_include_netlists.v" + +// Include testbench files +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v" diff --git a/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v b/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v deleted file mode 100644 index 8a43b0f..0000000 --- a/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:a13d2d93139126328833d3a1433c351eb044b0d4772ba56d214d65017a3e8c37 -size 608 diff --git a/TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v b/TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v new file mode 100644 index 0000000..377a9b1 --- /dev/null +++ b/TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v @@ -0,0 +1,13 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Include caravel gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_rtl_include_netlists.v" + +// Include testbench files +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"