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Merge pull request #23 from LNIS-Projects/xt_dev 

Misc Updates: OpenFPGA scripts, Benchmarks and Architecture
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS) 2020-11-17 15:21:10 -07:00 committed by GitHub
parent ffc072f36e 55db5d5aaf
commit 3c898ae5c8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
23 changed files with 198 additions and 28 deletions
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6
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -144,10 +144,10 @@
</fc>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top">clb.clk clb.reg_in clb.sc_in clb.reg_out clb.sc_out clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="left">clb.clk</loc>
<loc side="top">clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom"></loc>
<loc side="bottom">clb.reg_out clb.sc_out</loc>
</pinlocations>
</tile>
</tiles>

3
BENCHMARK/and2/and2.act Normal file
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@ -0,0 +1,3 @@
a 0.5 0.5
b 0.5 0.5
c 0.25 0.25

8
BENCHMARK/and2/and2.blif Normal file
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@ -0,0 +1,8 @@
.model and2
.inputs a b
.outputs c
.names a b c
11 1
.end

18
BENCHMARK/and2/and2.v Normal file
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@ -0,0 +1,18 @@
/////////////////////////////////////////
// Functionality: 2-input AND
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a & b;
endmodule

6
BENCHMARK/and2_latch/and2_latch.act Normal file
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@ -0,0 +1,6 @@
a 0.492800 0.201000
b 0.502000 0.197200
clk 0.500000 2.000000
d 0.240200 0.171200
c 0.240200 0.044100
n1 0.240200 0.044100

14
BENCHMARK/and2_latch/and2_latch.blif Normal file
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@ -0,0 +1,14 @@
# Benchmark "and2_latch" written by ABC on Wed Mar 11 10:36:28 2020
.model and2_latch
.inputs a b clk
.outputs c d
.latch n1 d re clk 0
.names a b c
11 1
.names c n1
1 1
.end

29
BENCHMARK/and2_latch/and2_latch.v Normal file
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@ -0,0 +1,29 @@
/////////////////////////////////////////
// Functionality: 2-input AND with clocked
// and combinational outputs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_latch(
a,
b,
clk,
c,
d);
input wire clk;
input wire a;
input wire b;
output wire c;
output reg d;
assign c = a & b;
always @(posedge clk) begin
d <= c;
end
endmodule

16
BENCHMARK/counter/counter.v Normal file
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@ -0,0 +1,16 @@
module counter(clk_counter, q_counter, rst_counter);
input clk_counter;
input rst_counter;
output [7:0] q_counter;
reg [7:0] q_counter;
always @ (posedge clk_counter)
begin
if(rst_counter)
q_counter <= 8'b00000000;
else
q_counter <= q_counter + 1;
end
endmodule

24
BENCHMARK/counter/counter_tb.v Normal file
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@ -0,0 +1,24 @@
module counter_tb;
reg clk_counter, rst_counter;
wire [7:0] q_counter;
counter_original C_1(
clk_counter,
q_counter,
rst_counter);
initial begin
#0 rst_counter = 1'b1; clk_counter = 1'b0;
#100 rst_counter = 1'b0;
end
always begin
#10 clk_counter = ~clk_counter;
end
initial begin
#5000 $stop;
end
endmodule

2
SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

48
SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml Normal file
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@ -0,0 +1,48 @@
<!-- Simulation Setting for OpenFPGA framework
This file will use
- a fixed operating clock frequency
- a fixed programming clock frequency
Note: all the numbers are tuned to STA results from physical layouts
-->
<openfpga_simulation_setting>
<clock_setting>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher
-->
<operating frequency="50e6" num_cycles="auto" slack="0.2"/>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual programming clock frequency could be higher
-->
<programming frequency="50e6"/>
</clock_setting>
<simulator_option>
<operating_condition temperature="25"/>
<output_log verbose="false" captab="false"/>
<accuracy type="abs" value="1e-13"/>
<runtime fast_simulation="true"/>
</simulator_option>
<monte_carlo num_simulation_points="2"/>
<measurement_setting>
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measurement_setting>
<stimulus>
<clock>
<rise slew_type="abs" slew_time="20e-12" />
<fall slew_type="abs" slew_time="20e-12" />
</clock>
<input>
<rise slew_type="abs" slew_time="25e-12" />
<fall slew_type="abs" slew_time="25e-12" />
</input>
</stimulus>
</openfpga_simulation_setting>

8
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
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@ -18,18 +18,18 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
[SYNTHESIS_PARAM]
bench0_top = and2

6
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
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@ -18,17 +18,17 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
[SYNTHESIS_PARAM]
bench0_top = and2

10
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -18,21 +18,23 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

4
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
View File

@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
@ -29,7 +29,7 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
[SYNTHESIS_PARAM]
bench0_top = and2

4
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
View File

@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
@ -28,7 +28,7 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
[SYNTHESIS_PARAM]
bench0_top = and2

8
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
View File

@ -18,10 +18,10 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml
@ -29,10 +29,12 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

0
TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v → TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v
View File

4
TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v → TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
View File

@ -9,7 +9,7 @@
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
@ -65,6 +65,6 @@
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
`endif

0
TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v → TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v
View File

4
TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v → TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
View File

@ -9,7 +9,7 @@
`timescale 1ns / 1ps
// ------ Include preprocessing flags -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
@ -59,5 +59,5 @@
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
`endif