diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 336743e..92ea39f 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -144,10 +144,10 @@ - - clb.clk clb.reg_in clb.sc_in clb.reg_out clb.sc_out clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.clk + clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i - + clb.reg_out clb.sc_out diff --git a/BENCHMARK/and2/and2.act b/BENCHMARK/and2/and2.act new file mode 100644 index 0000000..0f77bc6 --- /dev/null +++ b/BENCHMARK/and2/and2.act @@ -0,0 +1,3 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.25 diff --git a/BENCHMARK/and2/and2.blif b/BENCHMARK/and2/and2.blif new file mode 100644 index 0000000..d13bdc5 --- /dev/null +++ b/BENCHMARK/and2/and2.blif @@ -0,0 +1,8 @@ +.model and2 +.inputs a b +.outputs c + +.names a b c +11 1 + +.end diff --git a/BENCHMARK/and2/and2.v b/BENCHMARK/and2/and2.v new file mode 100644 index 0000000..a23293c --- /dev/null +++ b/BENCHMARK/and2/and2.v @@ -0,0 +1,18 @@ +///////////////////////////////////////// +// Functionality: 2-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and2( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a & b; + +endmodule diff --git a/BENCHMARK/and2_latch/and2_latch.act b/BENCHMARK/and2_latch/and2_latch.act new file mode 100644 index 0000000..61bbe1f --- /dev/null +++ b/BENCHMARK/and2_latch/and2_latch.act @@ -0,0 +1,6 @@ +a 0.492800 0.201000 +b 0.502000 0.197200 +clk 0.500000 2.000000 +d 0.240200 0.171200 +c 0.240200 0.044100 +n1 0.240200 0.044100 diff --git a/BENCHMARK/and2_latch/and2_latch.blif b/BENCHMARK/and2_latch/and2_latch.blif new file mode 100644 index 0000000..96450e3 --- /dev/null +++ b/BENCHMARK/and2_latch/and2_latch.blif @@ -0,0 +1,14 @@ +# Benchmark "and2_latch" written by ABC on Wed Mar 11 10:36:28 2020 +.model and2_latch +.inputs a b clk +.outputs c d + +.latch n1 d re clk 0 + +.names a b c +11 1 + +.names c n1 +1 1 + +.end diff --git a/BENCHMARK/and2_latch/and2_latch.v b/BENCHMARK/and2_latch/and2_latch.v new file mode 100644 index 0000000..135454d --- /dev/null +++ b/BENCHMARK/and2_latch/and2_latch.v @@ -0,0 +1,29 @@ +///////////////////////////////////////// +// Functionality: 2-input AND with clocked +// and combinational outputs +// Author: Xifan Tang +//////////////////////////////////////// + +`timescale 1ns / 1ps + +module and2_latch( + a, + b, + clk, + c, + d); + +input wire clk; + +input wire a; +input wire b; +output wire c; +output reg d; + +assign c = a & b; + +always @(posedge clk) begin + d <= c; +end + +endmodule diff --git a/BENCHMARK/counter/counter.v b/BENCHMARK/counter/counter.v new file mode 100644 index 0000000..2160532 --- /dev/null +++ b/BENCHMARK/counter/counter.v @@ -0,0 +1,16 @@ +module counter(clk_counter, q_counter, rst_counter); + + input clk_counter; + input rst_counter; + output [7:0] q_counter; + reg [7:0] q_counter; + + always @ (posedge clk_counter) + begin + if(rst_counter) + q_counter <= 8'b00000000; + else + q_counter <= q_counter + 1; + end + +endmodule diff --git a/BENCHMARK/counter/counter_tb.v b/BENCHMARK/counter/counter_tb.v new file mode 100644 index 0000000..accfd82 --- /dev/null +++ b/BENCHMARK/counter/counter_tb.v @@ -0,0 +1,24 @@ +module counter_tb; + + reg clk_counter, rst_counter; + wire [7:0] q_counter; + + counter_original C_1( + clk_counter, + q_counter, + rst_counter); + + initial begin + #0 rst_counter = 1'b1; clk_counter = 1'b0; + #100 rst_counter = 1'b0; + end + + always begin + #10 clk_counter = ~clk_counter; + end + + initial begin + #5000 $stop; + end + +endmodule \ No newline at end of file diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga index 971796f..1d9e37e 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - fabric hierarchy description for ICC2's hierarchical flow # - Timing/Design constraints # -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga index 2371794..b9b0b35 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - fabric hierarchy description for ICC2's hierarchical flow # - Timing/Design constraints # -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga index ecd657d..38e4631 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml new file mode 100644 index 0000000..92cf793 --- /dev/null +++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index f1e766c..222aee6 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -18,18 +18,18 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=12x12 openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 1313f52..24bc072 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -18,17 +18,17 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=12x12 openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index b3aefd4..4ff43fe 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -18,21 +18,23 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=12x12 openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr +openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v [SYNTHESIS_PARAM] bench0_top = and2 +bench1_top = and2_latch [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf index 3ab759c..5c2cfba 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -18,7 +18,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc @@ -29,7 +29,7 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf index 56a30e1..78f595f 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -18,7 +18,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_caravel_io_FPGA_2x2_fdhd_cc @@ -28,7 +28,7 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index 8f40d1f..fced52c 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -18,10 +18,10 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml @@ -29,10 +29,12 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v [SYNTHESIS_PARAM] bench0_top = and2 +bench1_top = and2_latch [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test= diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v similarity index 100% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v similarity index 97% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 6e71490..099b963 100644 --- a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/define_simulation.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/define_simulation.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" @@ -65,6 +65,6 @@ `endif `ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" `endif diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v similarity index 100% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v similarity index 97% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 554c65c..5c95b31 100644 --- a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // ------ Include preprocessing flags ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/define_simulation.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" @@ -59,5 +59,5 @@ `endif `ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" `endif