riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Updated design with new architecure and merged grid_io

This commit is contained in:
Ganesh Gore 2020-11-06 22:35:31 -07:00
parent 89d42cc03d
commit 31a73a42ba
152 changed files with 155135 additions and 228166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
View File

@ -4,3 +4,5 @@
**/*_task/run001 **/*_task/run001
**/*_task/latest **/*_task/latest
**/*_task/skywater **/*_task/skywater
**/*_Verilog/SRC_Skeleton
**/*_Verilog/SRCBackup

1
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt Normal file
View File

@ -0,0 +1 @@
{"grid_clb": ["grid_clb_1__1_", "grid_clb_1__2_", "grid_clb_2__1_", "grid_clb_2__2_"], "grid_io_top": ["grid_io_top_1__3_", "grid_io_top_2__3_"], "grid_io_right": ["grid_io_right_3__1_", "grid_io_right_3__2_"], "grid_io_bottom": ["grid_io_bottom_1__0_", "grid_io_bottom_2__0_"], "grid_io_left": ["grid_io_left_0__1_", "grid_io_left_0__2_"], "sb_0__0_": ["sb_0__0_"], "sb_0__1_": ["sb_0__1_"], "sb_0__2_": ["sb_0__2_"], "sb_1__0_": ["sb_1__0_"], "sb_1__1_": ["sb_1__1_"], "sb_1__2_": ["sb_1__2_"], "sb_2__0_": ["sb_2__0_"], "sb_2__1_": ["sb_2__1_"], "sb_2__2_": ["sb_2__2_"], "cbx_1__0_": ["cbx_1__0_", "cbx_2__0_"], "cbx_1__1_": ["cbx_1__1_", "cbx_2__1_"], "cbx_1__2_": ["cbx_1__2_", "cbx_2__2_"], "cby_0__1_": ["cby_0__1_", "cby_0__2_"], "cby_1__1_": ["cby_1__1_", "cby_1__2_"], "cby_2__1_": ["cby_2__1_", "cby_2__2_"], "direct_interc": ["direct_interc_0_", "direct_interc_1_", "direct_interc_2_", "direct_interc_3_", "direct_interc_4_", "direct_interc_5_"]}

15
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v
View File

@ -18,9 +18,9 @@
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/std_cell_extract.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
// //
`include "./SRC/sub_module/inv_buf_passgate.v" `include "./SRC/sub_module/inv_buf_passgate.v"
`include "./SRC/sub_module/arch_encoder.v" `include "./SRC/sub_module/arch_encoder.v"
@ -39,10 +39,10 @@
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" `include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle.v" `include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
`include "./SRC/lb/logical_tile_clb_mode_clb_.v" `include "./SRC/lb/logical_tile_clb_mode_clb_.v"
`include "./SRC/lb/grid_io_top.v" `include "./SRC/lb/grid_io_top_top.v"
`include "./SRC/lb/grid_io_right.v" `include "./SRC/lb/grid_io_right_right.v"
`include "./SRC/lb/grid_io_bottom.v" `include "./SRC/lb/grid_io_bottom_bottom.v"
`include "./SRC/lb/grid_io_left.v" `include "./SRC/lb/grid_io_left_left.v"
`include "./SRC/lb/grid_clb.v" `include "./SRC/lb/grid_clb.v"
// //
@ -60,6 +60,7 @@
`include "./SRC/routing/cbx_1__2_.v" `include "./SRC/routing/cbx_1__2_.v"
`include "./SRC/routing/cby_0__1_.v" `include "./SRC/routing/cby_0__1_.v"
`include "./SRC/routing/cby_1__1_.v" `include "./SRC/routing/cby_1__1_.v"
`include "./SRC/routing/cby_2__1_.v"
// //
`include "./SRC/fpga_top.v" `include "./SRC/fpga_top.v"

2757
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v
View File

File diff suppressed because it is too large Load Diff

1938
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v
View File

File diff suppressed because it is too large Load Diff

414
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v
View File

@ -1,292 +1,138 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module grid_clb(prog_clk,
Test_en,
clk,
top_width_0_height_0__pin_32_,
top_width_0_height_0__pin_33_,
right_width_0_height_0__pin_0_,
right_width_0_height_0__pin_1_,
right_width_0_height_0__pin_2_,
right_width_0_height_0__pin_3_,
right_width_0_height_0__pin_4_,
right_width_0_height_0__pin_5_,
right_width_0_height_0__pin_6_,
right_width_0_height_0__pin_7_,
right_width_0_height_0__pin_8_,
right_width_0_height_0__pin_9_,
right_width_0_height_0__pin_10_,
right_width_0_height_0__pin_11_,
right_width_0_height_0__pin_12_,
right_width_0_height_0__pin_13_,
right_width_0_height_0__pin_14_,
right_width_0_height_0__pin_15_,
bottom_width_0_height_0__pin_16_,
bottom_width_0_height_0__pin_17_,
bottom_width_0_height_0__pin_18_,
bottom_width_0_height_0__pin_19_,
bottom_width_0_height_0__pin_20_,
bottom_width_0_height_0__pin_21_,
bottom_width_0_height_0__pin_22_,
bottom_width_0_height_0__pin_23_,
bottom_width_0_height_0__pin_24_,
bottom_width_0_height_0__pin_25_,
bottom_width_0_height_0__pin_26_,
bottom_width_0_height_0__pin_27_,
bottom_width_0_height_0__pin_28_,
bottom_width_0_height_0__pin_29_,
bottom_width_0_height_0__pin_30_,
bottom_width_0_height_0__pin_31_,
left_width_0_height_0__pin_52_,
ccff_head,
right_width_0_height_0__pin_34_upper,
right_width_0_height_0__pin_34_lower,
right_width_0_height_0__pin_35_upper,
right_width_0_height_0__pin_35_lower,
right_width_0_height_0__pin_36_upper,
right_width_0_height_0__pin_36_lower,
right_width_0_height_0__pin_37_upper,
right_width_0_height_0__pin_37_lower,
right_width_0_height_0__pin_38_upper,
right_width_0_height_0__pin_38_lower,
right_width_0_height_0__pin_39_upper,
right_width_0_height_0__pin_39_lower,
right_width_0_height_0__pin_40_upper,
right_width_0_height_0__pin_40_lower,
right_width_0_height_0__pin_41_upper,
right_width_0_height_0__pin_41_lower,
bottom_width_0_height_0__pin_42_upper,
bottom_width_0_height_0__pin_42_lower,
bottom_width_0_height_0__pin_43_upper,
bottom_width_0_height_0__pin_43_lower,
bottom_width_0_height_0__pin_44_upper,
bottom_width_0_height_0__pin_44_lower,
bottom_width_0_height_0__pin_45_upper,
bottom_width_0_height_0__pin_45_lower,
bottom_width_0_height_0__pin_46_upper,
bottom_width_0_height_0__pin_46_lower,
bottom_width_0_height_0__pin_47_upper,
bottom_width_0_height_0__pin_47_lower,
bottom_width_0_height_0__pin_48_upper,
bottom_width_0_height_0__pin_48_lower,
bottom_width_0_height_0__pin_49_upper,
bottom_width_0_height_0__pin_49_lower,
bottom_width_0_height_0__pin_50_,
bottom_width_0_height_0__pin_51_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:0] clk;
//
input [0:0] top_width_0_height_0__pin_32_;
//
input [0:0] top_width_0_height_0__pin_33_;
//
input [0:0] right_width_0_height_0__pin_0_;
//
input [0:0] right_width_0_height_0__pin_1_;
//
input [0:0] right_width_0_height_0__pin_2_;
//
input [0:0] right_width_0_height_0__pin_3_;
//
input [0:0] right_width_0_height_0__pin_4_;
//
input [0:0] right_width_0_height_0__pin_5_;
//
input [0:0] right_width_0_height_0__pin_6_;
//
input [0:0] right_width_0_height_0__pin_7_;
//
input [0:0] right_width_0_height_0__pin_8_;
//
input [0:0] right_width_0_height_0__pin_9_;
//
input [0:0] right_width_0_height_0__pin_10_;
//
input [0:0] right_width_0_height_0__pin_11_;
//
input [0:0] right_width_0_height_0__pin_12_;
//
input [0:0] right_width_0_height_0__pin_13_;
//
input [0:0] right_width_0_height_0__pin_14_;
//
input [0:0] right_width_0_height_0__pin_15_;
//
input [0:0] bottom_width_0_height_0__pin_16_;
//
input [0:0] bottom_width_0_height_0__pin_17_;
//
input [0:0] bottom_width_0_height_0__pin_18_;
//
input [0:0] bottom_width_0_height_0__pin_19_;
//
input [0:0] bottom_width_0_height_0__pin_20_;
//
input [0:0] bottom_width_0_height_0__pin_21_;
//
input [0:0] bottom_width_0_height_0__pin_22_;
//
input [0:0] bottom_width_0_height_0__pin_23_;
//
input [0:0] bottom_width_0_height_0__pin_24_;
//
input [0:0] bottom_width_0_height_0__pin_25_;
//
input [0:0] bottom_width_0_height_0__pin_26_;
//
input [0:0] bottom_width_0_height_0__pin_27_;
//
input [0:0] bottom_width_0_height_0__pin_28_;
//
input [0:0] bottom_width_0_height_0__pin_29_;
//
input [0:0] bottom_width_0_height_0__pin_30_;
//
input [0:0] bottom_width_0_height_0__pin_31_;
//
input [0:0] left_width_0_height_0__pin_52_;
//
input [0:0] ccff_head;
//
output [0:0] right_width_0_height_0__pin_34_upper;
//
output [0:0] right_width_0_height_0__pin_34_lower;
//
output [0:0] right_width_0_height_0__pin_35_upper;
//
output [0:0] right_width_0_height_0__pin_35_lower;
//
output [0:0] right_width_0_height_0__pin_36_upper;
//
output [0:0] right_width_0_height_0__pin_36_lower;
//
output [0:0] right_width_0_height_0__pin_37_upper;
//
output [0:0] right_width_0_height_0__pin_37_lower;
//
output [0:0] right_width_0_height_0__pin_38_upper;
//
output [0:0] right_width_0_height_0__pin_38_lower;
//
output [0:0] right_width_0_height_0__pin_39_upper;
//
output [0:0] right_width_0_height_0__pin_39_lower;
//
output [0:0] right_width_0_height_0__pin_40_upper;
//
output [0:0] right_width_0_height_0__pin_40_lower;
//
output [0:0] right_width_0_height_0__pin_41_upper;
//
output [0:0] right_width_0_height_0__pin_41_lower;
//
output [0:0] bottom_width_0_height_0__pin_42_upper;
//
output [0:0] bottom_width_0_height_0__pin_42_lower;
//
output [0:0] bottom_width_0_height_0__pin_43_upper;
//
output [0:0] bottom_width_0_height_0__pin_43_lower;
//
output [0:0] bottom_width_0_height_0__pin_44_upper;
//
output [0:0] bottom_width_0_height_0__pin_44_lower;
//
output [0:0] bottom_width_0_height_0__pin_45_upper;
//
output [0:0] bottom_width_0_height_0__pin_45_lower;
//
output [0:0] bottom_width_0_height_0__pin_46_upper;
//
output [0:0] bottom_width_0_height_0__pin_46_lower;
//
output [0:0] bottom_width_0_height_0__pin_47_upper;
//
output [0:0] bottom_width_0_height_0__pin_47_lower;
//
output [0:0] bottom_width_0_height_0__pin_48_upper;
//
output [0:0] bottom_width_0_height_0__pin_48_lower;
//
output [0:0] bottom_width_0_height_0__pin_49_upper;
//
output [0:0] bottom_width_0_height_0__pin_49_lower;
//
output [0:0] bottom_width_0_height_0__pin_50_;
//
output [0:0] bottom_width_0_height_0__pin_51_;
//
output [0:0] ccff_tail;
//
//
// module grid_clb
// (
input [0:0] prog_clk,
input [0:0] Test_en,
input [0:0] clk,
input [0:0] top_width_0_height_0__pin_0_,
input [0:0] top_width_0_height_0__pin_1_,
input [0:0] top_width_0_height_0__pin_2_,
input [0:0] top_width_0_height_0__pin_3_,
input [0:0] top_width_0_height_0__pin_4_,
input [0:0] top_width_0_height_0__pin_5_,
input [0:0] top_width_0_height_0__pin_6_,
input [0:0] top_width_0_height_0__pin_7_,
input [0:0] top_width_0_height_0__pin_8_,
input [0:0] top_width_0_height_0__pin_9_,
input [0:0] top_width_0_height_0__pin_10_,
input [0:0] top_width_0_height_0__pin_11_,
input [0:0] top_width_0_height_0__pin_12_,
input [0:0] top_width_0_height_0__pin_13_,
input [0:0] top_width_0_height_0__pin_14_,
input [0:0] top_width_0_height_0__pin_15_,
input [0:0] top_width_0_height_0__pin_32_,
input [0:0] top_width_0_height_0__pin_33_,
input [0:0] right_width_0_height_0__pin_16_,
input [0:0] right_width_0_height_0__pin_17_,
input [0:0] right_width_0_height_0__pin_18_,
input [0:0] right_width_0_height_0__pin_19_,
input [0:0] right_width_0_height_0__pin_20_,
input [0:0] right_width_0_height_0__pin_21_,
input [0:0] right_width_0_height_0__pin_22_,
input [0:0] right_width_0_height_0__pin_23_,
input [0:0] right_width_0_height_0__pin_24_,
input [0:0] right_width_0_height_0__pin_25_,
input [0:0] right_width_0_height_0__pin_26_,
input [0:0] right_width_0_height_0__pin_27_,
input [0:0] right_width_0_height_0__pin_28_,
input [0:0] right_width_0_height_0__pin_29_,
input [0:0] right_width_0_height_0__pin_30_,
input [0:0] right_width_0_height_0__pin_31_,
input [0:0] left_width_0_height_0__pin_52_,
input [0:0] ccff_head,
output [0:0] top_width_0_height_0__pin_34_upper,
output [0:0] top_width_0_height_0__pin_34_lower,
output [0:0] top_width_0_height_0__pin_35_upper,
output [0:0] top_width_0_height_0__pin_35_lower,
output [0:0] top_width_0_height_0__pin_36_upper,
output [0:0] top_width_0_height_0__pin_36_lower,
output [0:0] top_width_0_height_0__pin_37_upper,
output [0:0] top_width_0_height_0__pin_37_lower,
output [0:0] top_width_0_height_0__pin_38_upper,
output [0:0] top_width_0_height_0__pin_38_lower,
output [0:0] top_width_0_height_0__pin_39_upper,
output [0:0] top_width_0_height_0__pin_39_lower,
output [0:0] top_width_0_height_0__pin_40_upper,
output [0:0] top_width_0_height_0__pin_40_lower,
output [0:0] top_width_0_height_0__pin_41_upper,
output [0:0] top_width_0_height_0__pin_41_lower,
output [0:0] right_width_0_height_0__pin_42_upper,
output [0:0] right_width_0_height_0__pin_42_lower,
output [0:0] right_width_0_height_0__pin_43_upper,
output [0:0] right_width_0_height_0__pin_43_lower,
output [0:0] right_width_0_height_0__pin_44_upper,
output [0:0] right_width_0_height_0__pin_44_lower,
output [0:0] right_width_0_height_0__pin_45_upper,
output [0:0] right_width_0_height_0__pin_45_lower,
output [0:0] right_width_0_height_0__pin_46_upper,
output [0:0] right_width_0_height_0__pin_46_lower,
output [0:0] right_width_0_height_0__pin_47_upper,
output [0:0] right_width_0_height_0__pin_47_lower,
output [0:0] right_width_0_height_0__pin_48_upper,
output [0:0] right_width_0_height_0__pin_48_lower,
output [0:0] right_width_0_height_0__pin_49_upper,
output [0:0] right_width_0_height_0__pin_49_lower,
output [0:0] bottom_width_0_height_0__pin_50_,
output [0:0] bottom_width_0_height_0__pin_51_,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0];
assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0];
assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0];
assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0];
assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0];
assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0];
assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0];
assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0];
assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0];
assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0];
assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0];
assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0];
assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0];
assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0];
assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0];
assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
logical_tile_clb_mode_clb_
logical_tile_clb_mode_clb__0
(
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }),
.clb_I0i(top_width_0_height_0__pin_3_[0]),
.clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }),
.clb_I1i(top_width_0_height_0__pin_7_[0]),
.clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }),
.clb_I2i(top_width_0_height_0__pin_11_[0]),
.clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }),
.clb_I3i(top_width_0_height_0__pin_15_[0]),
.clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }),
.clb_I4i(right_width_0_height_0__pin_19_[0]),
.clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }),
.clb_I5i(right_width_0_height_0__pin_23_[0]),
.clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }),
.clb_I6i(right_width_0_height_0__pin_27_[0]),
.clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }),
.clb_I7i(right_width_0_height_0__pin_31_[0]),
.clb_regin(top_width_0_height_0__pin_32_[0]),
.clb_sc_in(SC_IN_TOP),
.clb_clk(left_width_0_height_0__pin_52_[0]),
.ccff_head(ccff_head[0]),
.clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }),
.clb_regout(bottom_width_0_height_0__pin_50_[0]),
.clb_sc_out(SC_OUT_BOT),
.ccff_tail(ccff_tail[0])
);
//
//
//
assign right_width_0_height_0__pin_34_lower[0] = right_width_0_height_0__pin_34_upper[0];
assign right_width_0_height_0__pin_35_lower[0] = right_width_0_height_0__pin_35_upper[0];
assign right_width_0_height_0__pin_36_lower[0] = right_width_0_height_0__pin_36_upper[0];
assign right_width_0_height_0__pin_37_lower[0] = right_width_0_height_0__pin_37_upper[0];
assign right_width_0_height_0__pin_38_lower[0] = right_width_0_height_0__pin_38_upper[0];
assign right_width_0_height_0__pin_39_lower[0] = right_width_0_height_0__pin_39_upper[0];
assign right_width_0_height_0__pin_40_lower[0] = right_width_0_height_0__pin_40_upper[0];
assign right_width_0_height_0__pin_41_lower[0] = right_width_0_height_0__pin_41_upper[0];
assign bottom_width_0_height_0__pin_42_lower[0] = bottom_width_0_height_0__pin_42_upper[0];
assign bottom_width_0_height_0__pin_43_lower[0] = bottom_width_0_height_0__pin_43_upper[0];
assign bottom_width_0_height_0__pin_44_lower[0] = bottom_width_0_height_0__pin_44_upper[0];
assign bottom_width_0_height_0__pin_45_lower[0] = bottom_width_0_height_0__pin_45_upper[0];
assign bottom_width_0_height_0__pin_46_lower[0] = bottom_width_0_height_0__pin_46_upper[0];
assign bottom_width_0_height_0__pin_47_lower[0] = bottom_width_0_height_0__pin_47_upper[0];
assign bottom_width_0_height_0__pin_48_lower[0] = bottom_width_0_height_0__pin_48_upper[0];
assign bottom_width_0_height_0__pin_49_lower[0] = bottom_width_0_height_0__pin_49_upper[0];
//
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.clb_I0({right_width_0_height_0__pin_0_[0], right_width_0_height_0__pin_1_[0], right_width_0_height_0__pin_2_[0], right_width_0_height_0__pin_3_[0]}),
.clb_I1({right_width_0_height_0__pin_4_[0], right_width_0_height_0__pin_5_[0], right_width_0_height_0__pin_6_[0], right_width_0_height_0__pin_7_[0]}),
.clb_I2({right_width_0_height_0__pin_8_[0], right_width_0_height_0__pin_9_[0], right_width_0_height_0__pin_10_[0], right_width_0_height_0__pin_11_[0]}),
.clb_I3({right_width_0_height_0__pin_12_[0], right_width_0_height_0__pin_13_[0], right_width_0_height_0__pin_14_[0], right_width_0_height_0__pin_15_[0]}),
.clb_I4({bottom_width_0_height_0__pin_16_[0], bottom_width_0_height_0__pin_17_[0], bottom_width_0_height_0__pin_18_[0], bottom_width_0_height_0__pin_19_[0]}),
.clb_I5({bottom_width_0_height_0__pin_20_[0], bottom_width_0_height_0__pin_21_[0], bottom_width_0_height_0__pin_22_[0], bottom_width_0_height_0__pin_23_[0]}),
.clb_I6({bottom_width_0_height_0__pin_24_[0], bottom_width_0_height_0__pin_25_[0], bottom_width_0_height_0__pin_26_[0], bottom_width_0_height_0__pin_27_[0]}),
.clb_I7({bottom_width_0_height_0__pin_28_[0], bottom_width_0_height_0__pin_29_[0], bottom_width_0_height_0__pin_30_[0], bottom_width_0_height_0__pin_31_[0]}),
.clb_regin(top_width_0_height_0__pin_32_[0]),
.clb_scin(top_width_0_height_0__pin_33_[0]),
.clb_clk(left_width_0_height_0__pin_52_[0]),
.ccff_head(ccff_head[0]),
.clb_O({right_width_0_height_0__pin_34_upper[0], right_width_0_height_0__pin_35_upper[0], right_width_0_height_0__pin_36_upper[0], right_width_0_height_0__pin_37_upper[0], right_width_0_height_0__pin_38_upper[0], right_width_0_height_0__pin_39_upper[0], right_width_0_height_0__pin_40_upper[0], right_width_0_height_0__pin_41_upper[0], bottom_width_0_height_0__pin_42_upper[0], bottom_width_0_height_0__pin_43_upper[0], bottom_width_0_height_0__pin_44_upper[0], bottom_width_0_height_0__pin_45_upper[0], bottom_width_0_height_0__pin_46_upper[0], bottom_width_0_height_0__pin_47_upper[0], bottom_width_0_height_0__pin_48_upper[0], bottom_width_0_height_0__pin_49_upper[0]}),
.clb_regout(bottom_width_0_height_0__pin_50_[0]),
.clb_scout(bottom_width_0_height_0__pin_51_[0]),
.ccff_tail(ccff_tail[0]));
endmodule endmodule
//
//

137
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v
View File

@ -11,34 +11,76 @@
// //
// //
module grid_io_bottom(prog_clk, module grid_io_bottom(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y, top_width_0_height_0__pin_0_,
top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_,
ccff_head, top_width_0_height_0__pin_4_,
top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_6_,
top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_8_,
ccff_tail); top_width_0_height_0__pin_10_,
ccff_head,
top_width_0_height_0__pin_1_upper,
top_width_0_height_0__pin_1_lower,
top_width_0_height_0__pin_3_upper,
top_width_0_height_0__pin_3_lower,
top_width_0_height_0__pin_5_upper,
top_width_0_height_0__pin_5_lower,
top_width_0_height_0__pin_7_upper,
top_width_0_height_0__pin_7_lower,
top_width_0_height_0__pin_9_upper,
top_width_0_height_0__pin_9_lower,
top_width_0_height_0__pin_11_upper,
top_width_0_height_0__pin_11_lower,
ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] top_width_0_height_0__pin_0_; input [0:0] top_width_0_height_0__pin_0_;
// //
input [0:0] top_width_0_height_0__pin_2_;
//
input [0:0] top_width_0_height_0__pin_4_;
//
input [0:0] top_width_0_height_0__pin_6_;
//
input [0:0] top_width_0_height_0__pin_8_;
//
input [0:0] top_width_0_height_0__pin_10_;
//
input [0:0] ccff_head; input [0:0] ccff_head;
// //
output [0:0] top_width_0_height_0__pin_1_upper; output [0:0] top_width_0_height_0__pin_1_upper;
// //
output [0:0] top_width_0_height_0__pin_1_lower; output [0:0] top_width_0_height_0__pin_1_lower;
// //
output [0:0] top_width_0_height_0__pin_3_upper;
//
output [0:0] top_width_0_height_0__pin_3_lower;
//
output [0:0] top_width_0_height_0__pin_5_upper;
//
output [0:0] top_width_0_height_0__pin_5_lower;
//
output [0:0] top_width_0_height_0__pin_7_upper;
//
output [0:0] top_width_0_height_0__pin_7_lower;
//
output [0:0] top_width_0_height_0__pin_9_upper;
//
output [0:0] top_width_0_height_0__pin_9_lower;
//
output [0:0] top_width_0_height_0__pin_11_upper;
//
output [0:0] top_width_0_height_0__pin_11_lower;
//
output [0:0] ccff_tail; output [0:0] ccff_tail;
// //
@ -49,22 +91,81 @@ output [0:0] ccff_tail;
// //
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
// //
// //
// //
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
// //
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]),
.io_outpad(top_width_0_height_0__pin_0_[0]), .io_outpad(top_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.io_inpad(top_width_0_height_0__pin_1_upper[0]), .io_inpad(top_width_0_height_0__pin_1_upper[0]),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(ccff_tail[0])); .ccff_tail(ccff_tail[0]));
endmodule endmodule

32
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v
View File

@ -11,25 +11,22 @@
// //
// //
module grid_io_left(prog_clk, module grid_io_left(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y, right_width_0_height_0__pin_0_,
right_width_0_height_0__pin_0_, ccff_head,
ccff_head, right_width_0_height_0__pin_1_upper,
right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower,
right_width_0_height_0__pin_1_lower, ccff_tail);
ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] right_width_0_height_0__pin_0_; input [0:0] right_width_0_height_0__pin_0_;
// //
@ -58,10 +55,9 @@ output [0:0] ccff_tail;
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]), .io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.io_inpad(right_width_0_height_0__pin_1_upper[0]), .io_inpad(right_width_0_height_0__pin_1_upper[0]),

32
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v
View File

@ -11,25 +11,22 @@
// //
// //
module grid_io_right(prog_clk, module grid_io_right(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y, left_width_0_height_0__pin_0_,
left_width_0_height_0__pin_0_, ccff_head,
ccff_head, left_width_0_height_0__pin_1_upper,
left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower,
left_width_0_height_0__pin_1_lower, ccff_tail);
ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] left_width_0_height_0__pin_0_; input [0:0] left_width_0_height_0__pin_0_;
// //
@ -58,10 +55,9 @@ output [0:0] ccff_tail;
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]), .io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.io_inpad(left_width_0_height_0__pin_1_upper[0]), .io_inpad(left_width_0_height_0__pin_1_upper[0]),

32
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v
View File

@ -11,25 +11,22 @@
// //
// //
module grid_io_top(prog_clk, module grid_io_top(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y, bottom_width_0_height_0__pin_0_,
bottom_width_0_height_0__pin_0_, ccff_head,
ccff_head, bottom_width_0_height_0__pin_1_upper,
bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower,
bottom_width_0_height_0__pin_1_lower, ccff_tail);
ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] bottom_width_0_height_0__pin_0_; input [0:0] bottom_width_0_height_0__pin_0_;
// //
@ -58,10 +55,9 @@ output [0:0] ccff_tail;
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]), .io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]), .io_inpad(bottom_width_0_height_0__pin_1_upper[0]),

192
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v
View File

@ -14,20 +14,28 @@ module logical_tile_clb_mode_clb_(prog_clk,
Test_en, Test_en,
clk, clk,
clb_I0, clb_I0,
clb_I0i,
clb_I1, clb_I1,
clb_I1i,
clb_I2, clb_I2,
clb_I2i,
clb_I3, clb_I3,
clb_I3i,
clb_I4, clb_I4,
clb_I4i,
clb_I5, clb_I5,
clb_I5i,
clb_I6, clb_I6,
clb_I6i,
clb_I7, clb_I7,
clb_I7i,
clb_regin, clb_regin,
clb_scin, clb_sc_in,
clb_clk, clb_clk,
ccff_head, ccff_head,
clb_O, clb_O,
clb_regout, clb_regout,
clb_scout, clb_sc_out,
ccff_tail); ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
@ -36,25 +44,41 @@ input [0:0] Test_en;
// //
input [0:0] clk; input [0:0] clk;
// //
input [0:3] clb_I0; input [0:2] clb_I0;
// //
input [0:3] clb_I1; input [0:0] clb_I0i;
// //
input [0:3] clb_I2; input [0:2] clb_I1;
// //
input [0:3] clb_I3; input [0:0] clb_I1i;
// //
input [0:3] clb_I4; input [0:2] clb_I2;
// //
input [0:3] clb_I5; input [0:0] clb_I2i;
// //
input [0:3] clb_I6; input [0:2] clb_I3;
// //
input [0:3] clb_I7; input [0:0] clb_I3i;
//
input [0:2] clb_I4;
//
input [0:0] clb_I4i;
//
input [0:2] clb_I5;
//
input [0:0] clb_I5i;
//
input [0:2] clb_I6;
//
input [0:0] clb_I6i;
//
input [0:2] clb_I7;
//
input [0:0] clb_I7i;
// //
input [0:0] clb_regin; input [0:0] clb_regin;
// //
input [0:0] clb_scin; input [0:0] clb_sc_in;
// //
input [0:0] clb_clk; input [0:0] clb_clk;
// //
@ -64,25 +88,33 @@ output [0:15] clb_O;
// //
output [0:0] clb_regout; output [0:0] clb_regout;
// //
output [0:0] clb_scout; output [0:0] clb_sc_out;
// //
output [0:0] ccff_tail; output [0:0] ccff_tail;
// //
wire [0:3] clb_I0; wire [0:2] clb_I0;
wire [0:3] clb_I1; wire [0:0] clb_I0i;
wire [0:3] clb_I2; wire [0:2] clb_I1;
wire [0:3] clb_I3; wire [0:0] clb_I1i;
wire [0:3] clb_I4; wire [0:2] clb_I2;
wire [0:3] clb_I5; wire [0:0] clb_I2i;
wire [0:3] clb_I6; wire [0:2] clb_I3;
wire [0:3] clb_I7; wire [0:0] clb_I3i;
wire [0:2] clb_I4;
wire [0:0] clb_I4i;
wire [0:2] clb_I5;
wire [0:0] clb_I5i;
wire [0:2] clb_I6;
wire [0:0] clb_I6i;
wire [0:2] clb_I7;
wire [0:0] clb_I7i;
wire [0:0] clb_regin; wire [0:0] clb_regin;
wire [0:0] clb_scin; wire [0:0] clb_sc_in;
wire [0:0] clb_clk; wire [0:0] clb_clk;
wire [0:15] clb_O; wire [0:15] clb_O;
wire [0:0] clb_regout; wire [0:0] clb_regout;
wire [0:0] clb_scout; wire [0:0] clb_sc_out;
// //
@ -149,34 +181,34 @@ wire [0:0] direct_interc_73_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out; wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout; wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
// //
// //
@ -189,12 +221,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}), .fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}),
.fle_regin(direct_interc_22_out[0]), .fle_regin(direct_interc_22_out[0]),
.fle_scin(direct_interc_23_out[0]), .fle_sc_in(direct_interc_23_out[0]),
.fle_clk(direct_interc_24_out[0]), .fle_clk(direct_interc_24_out[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_0_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
@ -203,12 +235,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}), .fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}),
.fle_regin(direct_interc_29_out[0]), .fle_regin(direct_interc_29_out[0]),
.fle_scin(direct_interc_30_out[0]), .fle_sc_in(direct_interc_30_out[0]),
.fle_clk(direct_interc_31_out[0]), .fle_clk(direct_interc_31_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_1_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
@ -217,12 +249,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}), .fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}),
.fle_regin(direct_interc_36_out[0]), .fle_regin(direct_interc_36_out[0]),
.fle_scin(direct_interc_37_out[0]), .fle_sc_in(direct_interc_37_out[0]),
.fle_clk(direct_interc_38_out[0]), .fle_clk(direct_interc_38_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_2_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
@ -231,12 +263,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}), .fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}),
.fle_regin(direct_interc_43_out[0]), .fle_regin(direct_interc_43_out[0]),
.fle_scin(direct_interc_44_out[0]), .fle_sc_in(direct_interc_44_out[0]),
.fle_clk(direct_interc_45_out[0]), .fle_clk(direct_interc_45_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_3_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
@ -245,12 +277,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}), .fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}),
.fle_regin(direct_interc_50_out[0]), .fle_regin(direct_interc_50_out[0]),
.fle_scin(direct_interc_51_out[0]), .fle_sc_in(direct_interc_51_out[0]),
.fle_clk(direct_interc_52_out[0]), .fle_clk(direct_interc_52_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_4_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
@ -259,12 +291,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}), .fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}),
.fle_regin(direct_interc_57_out[0]), .fle_regin(direct_interc_57_out[0]),
.fle_scin(direct_interc_58_out[0]), .fle_sc_in(direct_interc_58_out[0]),
.fle_clk(direct_interc_59_out[0]), .fle_clk(direct_interc_59_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_5_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
@ -273,12 +305,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}), .fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}),
.fle_regin(direct_interc_64_out[0]), .fle_regin(direct_interc_64_out[0]),
.fle_scin(direct_interc_65_out[0]), .fle_sc_in(direct_interc_65_out[0]),
.fle_clk(direct_interc_66_out[0]), .fle_clk(direct_interc_66_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_6_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0])); .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
@ -287,12 +319,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.clk(clk[0]), .clk(clk[0]),
.fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}), .fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}),
.fle_regin(direct_interc_71_out[0]), .fle_regin(direct_interc_71_out[0]),
.fle_scin(direct_interc_72_out[0]), .fle_sc_in(direct_interc_72_out[0]),
.fle_clk(direct_interc_73_out[0]), .fle_clk(direct_interc_73_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]), .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]), .fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]), .fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]),
.fle_scout(logical_tile_clb_mode_default__fle_7_fle_scout[0]), .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.ccff_tail(ccff_tail[0])); .ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ ( direct_interc direct_interc_0_ (
@ -364,11 +396,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(clb_regout[0])); .out(clb_regout[0]));
direct_interc direct_interc_17_ ( direct_interc direct_interc_17_ (
.in(logical_tile_clb_mode_default__fle_7_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.out(clb_scout[0])); .out(clb_sc_out[0]));
direct_interc direct_interc_18_ ( direct_interc direct_interc_18_ (
.in(clb_I0[0]), .in(clb_I0[2]),
.out(direct_interc_18_out[0])); .out(direct_interc_18_out[0]));
direct_interc direct_interc_19_ ( direct_interc direct_interc_19_ (
@ -376,11 +408,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_19_out[0])); .out(direct_interc_19_out[0]));
direct_interc direct_interc_20_ ( direct_interc direct_interc_20_ (
.in(clb_I0[2]), .in(clb_I0[0]),
.out(direct_interc_20_out[0])); .out(direct_interc_20_out[0]));
direct_interc direct_interc_21_ ( direct_interc direct_interc_21_ (
.in(clb_I0[3]), .in(clb_I0i[0]),
.out(direct_interc_21_out[0])); .out(direct_interc_21_out[0]));
direct_interc direct_interc_22_ ( direct_interc direct_interc_22_ (
@ -388,7 +420,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_22_out[0])); .out(direct_interc_22_out[0]));
direct_interc direct_interc_23_ ( direct_interc direct_interc_23_ (
.in(clb_scin[0]), .in(clb_sc_in[0]),
.out(direct_interc_23_out[0])); .out(direct_interc_23_out[0]));
direct_interc direct_interc_24_ ( direct_interc direct_interc_24_ (
@ -396,7 +428,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_24_out[0])); .out(direct_interc_24_out[0]));
direct_interc direct_interc_25_ ( direct_interc direct_interc_25_ (
.in(clb_I1[0]), .in(clb_I1[2]),
.out(direct_interc_25_out[0])); .out(direct_interc_25_out[0]));
direct_interc direct_interc_26_ ( direct_interc direct_interc_26_ (
@ -404,11 +436,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_26_out[0])); .out(direct_interc_26_out[0]));
direct_interc direct_interc_27_ ( direct_interc direct_interc_27_ (
.in(clb_I1[2]), .in(clb_I1[0]),
.out(direct_interc_27_out[0])); .out(direct_interc_27_out[0]));
direct_interc direct_interc_28_ ( direct_interc direct_interc_28_ (
.in(clb_I1[3]), .in(clb_I1i[0]),
.out(direct_interc_28_out[0])); .out(direct_interc_28_out[0]));
direct_interc direct_interc_29_ ( direct_interc direct_interc_29_ (
@ -416,7 +448,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_29_out[0])); .out(direct_interc_29_out[0]));
direct_interc direct_interc_30_ ( direct_interc direct_interc_30_ (
.in(logical_tile_clb_mode_default__fle_0_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.out(direct_interc_30_out[0])); .out(direct_interc_30_out[0]));
direct_interc direct_interc_31_ ( direct_interc direct_interc_31_ (
@ -424,7 +456,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_31_out[0])); .out(direct_interc_31_out[0]));
direct_interc direct_interc_32_ ( direct_interc direct_interc_32_ (
.in(clb_I2[0]), .in(clb_I2[2]),
.out(direct_interc_32_out[0])); .out(direct_interc_32_out[0]));
direct_interc direct_interc_33_ ( direct_interc direct_interc_33_ (
@ -432,11 +464,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_33_out[0])); .out(direct_interc_33_out[0]));
direct_interc direct_interc_34_ ( direct_interc direct_interc_34_ (
.in(clb_I2[2]), .in(clb_I2[0]),
.out(direct_interc_34_out[0])); .out(direct_interc_34_out[0]));
direct_interc direct_interc_35_ ( direct_interc direct_interc_35_ (
.in(clb_I2[3]), .in(clb_I2i[0]),
.out(direct_interc_35_out[0])); .out(direct_interc_35_out[0]));
direct_interc direct_interc_36_ ( direct_interc direct_interc_36_ (
@ -444,7 +476,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_36_out[0])); .out(direct_interc_36_out[0]));
direct_interc direct_interc_37_ ( direct_interc direct_interc_37_ (
.in(logical_tile_clb_mode_default__fle_1_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.out(direct_interc_37_out[0])); .out(direct_interc_37_out[0]));
direct_interc direct_interc_38_ ( direct_interc direct_interc_38_ (
@ -452,7 +484,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_38_out[0])); .out(direct_interc_38_out[0]));
direct_interc direct_interc_39_ ( direct_interc direct_interc_39_ (
.in(clb_I3[0]), .in(clb_I3[2]),
.out(direct_interc_39_out[0])); .out(direct_interc_39_out[0]));
direct_interc direct_interc_40_ ( direct_interc direct_interc_40_ (
@ -460,11 +492,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_40_out[0])); .out(direct_interc_40_out[0]));
direct_interc direct_interc_41_ ( direct_interc direct_interc_41_ (
.in(clb_I3[2]), .in(clb_I3[0]),
.out(direct_interc_41_out[0])); .out(direct_interc_41_out[0]));
direct_interc direct_interc_42_ ( direct_interc direct_interc_42_ (
.in(clb_I3[3]), .in(clb_I3i[0]),
.out(direct_interc_42_out[0])); .out(direct_interc_42_out[0]));
direct_interc direct_interc_43_ ( direct_interc direct_interc_43_ (
@ -472,7 +504,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_43_out[0])); .out(direct_interc_43_out[0]));
direct_interc direct_interc_44_ ( direct_interc direct_interc_44_ (
.in(logical_tile_clb_mode_default__fle_2_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.out(direct_interc_44_out[0])); .out(direct_interc_44_out[0]));
direct_interc direct_interc_45_ ( direct_interc direct_interc_45_ (
@ -480,7 +512,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_45_out[0])); .out(direct_interc_45_out[0]));
direct_interc direct_interc_46_ ( direct_interc direct_interc_46_ (
.in(clb_I4[0]), .in(clb_I4[2]),
.out(direct_interc_46_out[0])); .out(direct_interc_46_out[0]));
direct_interc direct_interc_47_ ( direct_interc direct_interc_47_ (
@ -488,11 +520,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_47_out[0])); .out(direct_interc_47_out[0]));
direct_interc direct_interc_48_ ( direct_interc direct_interc_48_ (
.in(clb_I4[2]), .in(clb_I4[0]),
.out(direct_interc_48_out[0])); .out(direct_interc_48_out[0]));
direct_interc direct_interc_49_ ( direct_interc direct_interc_49_ (
.in(clb_I4[3]), .in(clb_I4i[0]),
.out(direct_interc_49_out[0])); .out(direct_interc_49_out[0]));
direct_interc direct_interc_50_ ( direct_interc direct_interc_50_ (
@ -500,7 +532,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_50_out[0])); .out(direct_interc_50_out[0]));
direct_interc direct_interc_51_ ( direct_interc direct_interc_51_ (
.in(logical_tile_clb_mode_default__fle_3_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.out(direct_interc_51_out[0])); .out(direct_interc_51_out[0]));
direct_interc direct_interc_52_ ( direct_interc direct_interc_52_ (
@ -508,7 +540,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_52_out[0])); .out(direct_interc_52_out[0]));
direct_interc direct_interc_53_ ( direct_interc direct_interc_53_ (
.in(clb_I5[0]), .in(clb_I5[2]),
.out(direct_interc_53_out[0])); .out(direct_interc_53_out[0]));
direct_interc direct_interc_54_ ( direct_interc direct_interc_54_ (
@ -516,11 +548,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_54_out[0])); .out(direct_interc_54_out[0]));
direct_interc direct_interc_55_ ( direct_interc direct_interc_55_ (
.in(clb_I5[2]), .in(clb_I5[0]),
.out(direct_interc_55_out[0])); .out(direct_interc_55_out[0]));
direct_interc direct_interc_56_ ( direct_interc direct_interc_56_ (
.in(clb_I5[3]), .in(clb_I5i[0]),
.out(direct_interc_56_out[0])); .out(direct_interc_56_out[0]));
direct_interc direct_interc_57_ ( direct_interc direct_interc_57_ (
@ -528,7 +560,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_57_out[0])); .out(direct_interc_57_out[0]));
direct_interc direct_interc_58_ ( direct_interc direct_interc_58_ (
.in(logical_tile_clb_mode_default__fle_4_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.out(direct_interc_58_out[0])); .out(direct_interc_58_out[0]));
direct_interc direct_interc_59_ ( direct_interc direct_interc_59_ (
@ -536,7 +568,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_59_out[0])); .out(direct_interc_59_out[0]));
direct_interc direct_interc_60_ ( direct_interc direct_interc_60_ (
.in(clb_I6[0]), .in(clb_I6[2]),
.out(direct_interc_60_out[0])); .out(direct_interc_60_out[0]));
direct_interc direct_interc_61_ ( direct_interc direct_interc_61_ (
@ -544,11 +576,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_61_out[0])); .out(direct_interc_61_out[0]));
direct_interc direct_interc_62_ ( direct_interc direct_interc_62_ (
.in(clb_I6[2]), .in(clb_I6[0]),
.out(direct_interc_62_out[0])); .out(direct_interc_62_out[0]));
direct_interc direct_interc_63_ ( direct_interc direct_interc_63_ (
.in(clb_I6[3]), .in(clb_I6i[0]),
.out(direct_interc_63_out[0])); .out(direct_interc_63_out[0]));
direct_interc direct_interc_64_ ( direct_interc direct_interc_64_ (
@ -556,7 +588,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_64_out[0])); .out(direct_interc_64_out[0]));
direct_interc direct_interc_65_ ( direct_interc direct_interc_65_ (
.in(logical_tile_clb_mode_default__fle_5_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.out(direct_interc_65_out[0])); .out(direct_interc_65_out[0]));
direct_interc direct_interc_66_ ( direct_interc direct_interc_66_ (
@ -564,7 +596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_66_out[0])); .out(direct_interc_66_out[0]));
direct_interc direct_interc_67_ ( direct_interc direct_interc_67_ (
.in(clb_I7[0]), .in(clb_I7[2]),
.out(direct_interc_67_out[0])); .out(direct_interc_67_out[0]));
direct_interc direct_interc_68_ ( direct_interc direct_interc_68_ (
@ -572,11 +604,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_68_out[0])); .out(direct_interc_68_out[0]));
direct_interc direct_interc_69_ ( direct_interc direct_interc_69_ (
.in(clb_I7[2]), .in(clb_I7[0]),
.out(direct_interc_69_out[0])); .out(direct_interc_69_out[0]));
direct_interc direct_interc_70_ ( direct_interc direct_interc_70_ (
.in(clb_I7[3]), .in(clb_I7i[0]),
.out(direct_interc_70_out[0])); .out(direct_interc_70_out[0]));
direct_interc direct_interc_71_ ( direct_interc direct_interc_71_ (
@ -584,7 +616,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout;
.out(direct_interc_71_out[0])); .out(direct_interc_71_out[0]));
direct_interc direct_interc_72_ ( direct_interc direct_interc_72_ (
.in(logical_tile_clb_mode_default__fle_6_fle_scout[0]), .in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.out(direct_interc_72_out[0])); .out(direct_interc_72_out[0]));
direct_interc direct_interc_73_ ( direct_interc direct_interc_73_ (

24
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v
View File

@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle(prog_clk,
clk, clk,
fle_in, fle_in,
fle_regin, fle_regin,
fle_scin, fle_sc_in,
fle_clk, fle_clk,
ccff_head, ccff_head,
fle_out, fle_out,
fle_regout, fle_regout,
fle_scout, fle_sc_out,
ccff_tail); ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
@ -33,7 +33,7 @@ input [0:3] fle_in;
// //
input [0:0] fle_regin; input [0:0] fle_regin;
// //
input [0:0] fle_scin; input [0:0] fle_sc_in;
// //
input [0:0] fle_clk; input [0:0] fle_clk;
// //
@ -43,18 +43,18 @@ output [0:1] fle_out;
// //
output [0:0] fle_regout; output [0:0] fle_regout;
// //
output [0:0] fle_scout; output [0:0] fle_sc_out;
// //
output [0:0] ccff_tail; output [0:0] ccff_tail;
// //
wire [0:3] fle_in; wire [0:3] fle_in;
wire [0:0] fle_regin; wire [0:0] fle_regin;
wire [0:0] fle_scin; wire [0:0] fle_sc_in;
wire [0:0] fle_clk; wire [0:0] fle_clk;
wire [0:1] fle_out; wire [0:1] fle_out;
wire [0:0] fle_regout; wire [0:0] fle_regout;
wire [0:0] fle_scout; wire [0:0] fle_sc_out;
// //
@ -71,7 +71,7 @@ wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out; wire [0:0] direct_interc_9_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
// //
// //
@ -84,12 +84,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco
.clk(clk[0]), .clk(clk[0]),
.fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}), .fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}),
.fabric_regin(direct_interc_8_out[0]), .fabric_regin(direct_interc_8_out[0]),
.fabric_scin(direct_interc_9_out[0]), .fabric_sc_in(direct_interc_9_out[0]),
.fabric_clk(direct_interc_10_out[0]), .fabric_clk(direct_interc_10_out[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]), .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), .fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]),
.fabric_scout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.ccff_tail(ccff_tail[0])); .ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ ( direct_interc direct_interc_0_ (
@ -105,8 +105,8 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco
.out(fle_regout[0])); .out(fle_regout[0]));
direct_interc direct_interc_3_ ( direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.out(fle_scout[0])); .out(fle_sc_out[0]));
direct_interc direct_interc_4_ ( direct_interc direct_interc_4_ (
.in(fle_in[0]), .in(fle_in[0]),
@ -129,7 +129,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco
.out(direct_interc_8_out[0])); .out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ ( direct_interc direct_interc_9_ (
.in(fle_scin[0]), .in(fle_sc_in[0]),
.out(direct_interc_9_out[0])); .out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ ( direct_interc direct_interc_10_ (

16
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
View File

@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk,
clk, clk,
fabric_in, fabric_in,
fabric_regin, fabric_regin,
fabric_scin, fabric_sc_in,
fabric_clk, fabric_clk,
ccff_head, ccff_head,
fabric_out, fabric_out,
fabric_regout, fabric_regout,
fabric_scout, fabric_sc_out,
ccff_tail); ccff_tail);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
@ -33,7 +33,7 @@ input [0:3] fabric_in;
// //
input [0:0] fabric_regin; input [0:0] fabric_regin;
// //
input [0:0] fabric_scin; input [0:0] fabric_sc_in;
// //
input [0:0] fabric_clk; input [0:0] fabric_clk;
// //
@ -43,18 +43,18 @@ output [0:1] fabric_out;
// //
output [0:0] fabric_regout; output [0:0] fabric_regout;
// //
output [0:0] fabric_scout; output [0:0] fabric_sc_out;
// //
output [0:0] ccff_tail; output [0:0] ccff_tail;
// //
wire [0:3] fabric_in; wire [0:3] fabric_in;
wire [0:0] fabric_regin; wire [0:0] fabric_regin;
wire [0:0] fabric_scin; wire [0:0] fabric_sc_in;
wire [0:0] fabric_clk; wire [0:0] fabric_clk;
wire [0:1] fabric_out; wire [0:1] fabric_out;
wire [0:0] fabric_regout; wire [0:0] fabric_regout;
wire [0:0] fabric_scout; wire [0:0] fabric_sc_out;
// //
@ -158,7 +158,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
direct_interc direct_interc_1_ ( direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_scout[0])); .out(fabric_sc_out[0]));
direct_interc direct_interc_2_ ( direct_interc direct_interc_2_ (
.in(fabric_in[0]), .in(fabric_in[0]),
@ -177,7 +177,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
.out(direct_interc_5_out[0])); .out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ ( direct_interc direct_interc_6_ (
.in(fabric_scin[0]), .in(fabric_sc_in[0]),
.out(direct_interc_6_out[0])); .out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ ( direct_interc direct_interc_7_ (

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
View File

@ -46,7 +46,7 @@ wire [0:0] ff_clk;
// //
// //
sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ (
.SCE(Test_en[0]), .SCE(Test_en[0]),
.CLK(clk[0]), .CLK(clk[0]),
.D(ff_D[0]), .D(ff_D[0]),

22
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v
View File

@ -11,10 +11,9 @@
// //
// //
module logical_tile_io_mode_io_(prog_clk, module logical_tile_io_mode_io_(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y,
io_outpad, io_outpad,
ccff_head, ccff_head,
io_inpad, io_inpad,
@ -22,13 +21,11 @@ module logical_tile_io_mode_io_(prog_clk,
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] io_outpad; input [0:0] io_outpad;
// //
@ -58,10 +55,9 @@ wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]),
.iopad_outpad(direct_interc_1_out[0]), .iopad_outpad(direct_interc_1_out[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),

40
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v
View File

@ -10,10 +10,9 @@
// //
module logical_tile_io_mode_physical__iopad(prog_clk, module logical_tile_io_mode_physical__iopad(prog_clk,
gfpga_pad_GPIO_A, gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_GPIO_IE, gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_GPIO_OE, gfpga_pad_EMBEDDED_IO_SOC_DIR,
gfpga_pad_GPIO_Y,
iopad_outpad, iopad_outpad,
ccff_head, ccff_head,
iopad_inpad, iopad_inpad,
@ -21,13 +20,11 @@ module logical_tile_io_mode_physical__iopad(prog_clk,
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //
output [0:0] gfpga_pad_GPIO_A; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
// //
output [0:0] gfpga_pad_GPIO_IE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
// //
output [0:0] gfpga_pad_GPIO_OE; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
inout [0:0] gfpga_pad_GPIO_Y;
// //
input [0:0] iopad_outpad; input [0:0] iopad_outpad;
// //
@ -47,29 +44,28 @@ wire [0:0] iopad_inpad;
// //
wire [0:0] GPIO_0_en; wire [0:0] EMBEDDED_IO_0_en;
wire [0:0] GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb;
// //
// //
// //
// //
GPIO GPIO_0_ ( EMBEDDED_IO EMBEDDED_IO_0_ (
.A(gfpga_pad_GPIO_A[0]), .SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.IE(gfpga_pad_GPIO_IE[0]), .SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.OE(gfpga_pad_GPIO_OE[0]), .SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.Y(gfpga_pad_GPIO_Y[0]), .FPGA_OUT(iopad_outpad[0]),
.in(iopad_outpad[0]), .FPGA_DIR(EMBEDDED_IO_0_en[0]),
.mem_out(GPIO_0_en[0]), .FPGA_IN(iopad_inpad[0]));
.out(iopad_inpad[0]));
GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]), .ccff_tail(ccff_tail[0]),
.mem_out(GPIO_0_en[0]), .mem_out(EMBEDDED_IO_0_en[0]),
.mem_outb(GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); .mem_outb(EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0]));
endmodule endmodule
// //

782
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v
View File

@ -1,534 +1,328 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module cbx_1__0_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_pin_16_,
top_grid_pin_17_,
top_grid_pin_18_,
top_grid_pin_19_,
top_grid_pin_20_,
top_grid_pin_21_,
top_grid_pin_22_,
top_grid_pin_23_,
top_grid_pin_24_,
top_grid_pin_25_,
top_grid_pin_26_,
top_grid_pin_27_,
top_grid_pin_28_,
top_grid_pin_29_,
top_grid_pin_30_,
top_grid_pin_31_,
bottom_grid_pin_0_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chanx_left_in;
//
input [0:19] chanx_right_in;
//
input [0:0] ccff_head;
//
output [0:19] chanx_left_out;
//
output [0:19] chanx_right_out;
//
output [0:0] top_grid_pin_16_;
//
output [0:0] top_grid_pin_17_;
//
output [0:0] top_grid_pin_18_;
//
output [0:0] top_grid_pin_19_;
//
output [0:0] top_grid_pin_20_;
//
output [0:0] top_grid_pin_21_;
//
output [0:0] top_grid_pin_22_;
//
output [0:0] top_grid_pin_23_;
//
output [0:0] top_grid_pin_24_;
//
output [0:0] top_grid_pin_25_;
//
output [0:0] top_grid_pin_26_;
//
output [0:0] top_grid_pin_27_;
//
output [0:0] top_grid_pin_28_;
//
output [0:0] top_grid_pin_29_;
//
output [0:0] top_grid_pin_30_;
//
output [0:0] top_grid_pin_31_;
//
output [0:0] bottom_grid_pin_0_;
//
output [0:0] ccff_tail;
//
//
// module cbx_1__0_
// (
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_10_,
output [0:0] ccff_tail,
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] top_width_0_height_0__pin_0_,
input [0:0] top_width_0_height_0__pin_2_,
input [0:0] top_width_0_height_0__pin_4_,
input [0:0] top_width_0_height_0__pin_6_,
input [0:0] top_width_0_height_0__pin_8_,
input [0:0] top_width_0_height_0__pin_10_,
output [0:0] top_width_0_height_0__pin_1_upper,
output [0:0] top_width_0_height_0__pin_1_lower,
output [0:0] top_width_0_height_0__pin_3_upper,
output [0:0] top_width_0_height_0__pin_3_lower,
output [0:0] top_width_0_height_0__pin_5_upper,
output [0:0] top_width_0_height_0__pin_5_lower,
output [0:0] top_width_0_height_0__pin_7_upper,
output [0:0] top_width_0_height_0__pin_7_lower,
output [0:0] top_width_0_height_0__pin_9_upper,
output [0:0] top_width_0_height_0__pin_9_lower,
output [0:0] top_width_0_height_0__pin_11_upper,
output [0:0] top_width_0_height_0__pin_11_lower,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire ccff_tail_mid;
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
wire [0:3] mux_tree_tapbuf_size10_0_sram; mux_tree_tapbuf_size10
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; mux_top_ipin_1
wire [0:3] mux_tree_tapbuf_size10_1_sram; (
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
wire [0:3] mux_tree_tapbuf_size10_2_sram; .sram(mux_tree_tapbuf_size10_1_sram[0:3]),
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
wire [0:3] mux_tree_tapbuf_size10_3_sram; .out(bottom_grid_pin_2_[0])
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; );
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
//
//
//
//
assign chanx_right_out[0] = chanx_left_in[0];
//
//
//
assign chanx_right_out[1] = chanx_left_in[1];
//
//
//
assign chanx_right_out[2] = chanx_left_in[2];
//
//
//
assign chanx_right_out[3] = chanx_left_in[3];
//
//
//
assign chanx_right_out[4] = chanx_left_in[4];
//
//
//
assign chanx_right_out[5] = chanx_left_in[5];
//
//
//
assign chanx_right_out[6] = chanx_left_in[6];
//
//
//
assign chanx_right_out[7] = chanx_left_in[7];
//
//
//
assign chanx_right_out[8] = chanx_left_in[8];
//
//
//
assign chanx_right_out[9] = chanx_left_in[9];
//
//
//
assign chanx_right_out[10] = chanx_left_in[10];
//
//
//
assign chanx_right_out[11] = chanx_left_in[11];
//
//
//
assign chanx_right_out[12] = chanx_left_in[12];
//
//
//
assign chanx_right_out[13] = chanx_left_in[13];
//
//
//
assign chanx_right_out[14] = chanx_left_in[14];
//
//
//
assign chanx_right_out[15] = chanx_left_in[15];
//
//
//
assign chanx_right_out[16] = chanx_left_in[16];
//
//
//
assign chanx_right_out[17] = chanx_left_in[17];
//
//
//
assign chanx_right_out[18] = chanx_left_in[18];
//
//
//
assign chanx_right_out[19] = chanx_left_in[19];
//
//
//
assign chanx_left_out[0] = chanx_right_in[0];
//
//
//
assign chanx_left_out[1] = chanx_right_in[1];
//
//
//
assign chanx_left_out[2] = chanx_right_in[2];
//
//
//
assign chanx_left_out[3] = chanx_right_in[3];
//
//
//
assign chanx_left_out[4] = chanx_right_in[4];
//
//
//
assign chanx_left_out[5] = chanx_right_in[5];
//
//
//
assign chanx_left_out[6] = chanx_right_in[6];
//
//
//
assign chanx_left_out[7] = chanx_right_in[7];
//
//
//
assign chanx_left_out[8] = chanx_right_in[8];
//
//
//
assign chanx_left_out[9] = chanx_right_in[9];
//
//
//
assign chanx_left_out[10] = chanx_right_in[10];
//
//
//
assign chanx_left_out[11] = chanx_right_in[11];
//
//
//
assign chanx_left_out[12] = chanx_right_in[12];
//
//
//
assign chanx_left_out[13] = chanx_right_in[13];
//
//
//
assign chanx_left_out[14] = chanx_right_in[14];
//
//
//
assign chanx_left_out[15] = chanx_right_in[15];
//
//
//
assign chanx_left_out[16] = chanx_right_in[16];
//
//
//
assign chanx_left_out[17] = chanx_right_in[17];
//
//
//
assign chanx_left_out[18] = chanx_right_in[18];
//
//
//
assign chanx_left_out[19] = chanx_right_in[19];
//
//
//
mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), mux_top_ipin_2
.sram(mux_tree_tapbuf_size10_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.out(top_grid_pin_16_[0])); .sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(top_grid_pin_17_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), mux_top_ipin_3
.sram(mux_tree_tapbuf_size10_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.out(top_grid_pin_20_[0])); .sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_5 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(top_grid_pin_21_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), mux_top_ipin_4
.sram(mux_tree_tapbuf_size10_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.out(top_grid_pin_24_[0])); .sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_9 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(top_grid_pin_25_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), mux_top_ipin_5
.sram(mux_tree_tapbuf_size10_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.out(top_grid_pin_28_[0])); .sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_13 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(top_grid_pin_29_[0]));
mux_tree_tapbuf_size10 mux_top_ipin_0 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), mem_top_ipin_0
.sram(mux_tree_tapbuf_size10_8_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(bottom_grid_pin_0_[0])); .ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_1
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); .ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_2
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); .ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_3
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); .ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_4
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); .ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_top_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), mem_top_ipin_5
.sram(mux_tree_tapbuf_size8_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_18_[0])); .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_3 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(top_grid_pin_19_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( logical_tile_io_mode_io_
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), logical_tile_io_mode_io__0
.sram(mux_tree_tapbuf_size8_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_22_[0])); .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(top_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_1_upper[0]),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_7 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(top_grid_pin_23_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( logical_tile_io_mode_io_
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), logical_tile_io_mode_io__1
.sram(mux_tree_tapbuf_size8_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_26_[0])); .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_11 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(top_grid_pin_27_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( logical_tile_io_mode_io_
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), logical_tile_io_mode_io__2
.sram(mux_tree_tapbuf_size8_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_30_[0])); .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_15 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(top_grid_pin_31_[0]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( logical_tile_io_mode_io_
.prog_clk(prog_clk[0]), logical_tile_io_mode_io__3
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( logical_tile_io_mode_io_
.prog_clk(prog_clk[0]), logical_tile_io_mode_io__4
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( logical_tile_io_mode_io_
.prog_clk(prog_clk[0]), logical_tile_io_mode_io__5
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(ccff_tail[0])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]));
endmodule endmodule
//

899
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v
View File

@ -1,515 +1,464 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module cbx_1__1_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_pin_16_,
top_grid_pin_17_,
top_grid_pin_18_,
top_grid_pin_19_,
top_grid_pin_20_,
top_grid_pin_21_,
top_grid_pin_22_,
top_grid_pin_23_,
top_grid_pin_24_,
top_grid_pin_25_,
top_grid_pin_26_,
top_grid_pin_27_,
top_grid_pin_28_,
top_grid_pin_29_,
top_grid_pin_30_,
top_grid_pin_31_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chanx_left_in;
//
input [0:19] chanx_right_in;
//
input [0:0] ccff_head;
//
output [0:19] chanx_left_out;
//
output [0:19] chanx_right_out;
//
output [0:0] top_grid_pin_16_;
//
output [0:0] top_grid_pin_17_;
//
output [0:0] top_grid_pin_18_;
//
output [0:0] top_grid_pin_19_;
//
output [0:0] top_grid_pin_20_;
//
output [0:0] top_grid_pin_21_;
//
output [0:0] top_grid_pin_22_;
//
output [0:0] top_grid_pin_23_;
//
output [0:0] top_grid_pin_24_;
//
output [0:0] top_grid_pin_25_;
//
output [0:0] top_grid_pin_26_;
//
output [0:0] top_grid_pin_27_;
//
output [0:0] top_grid_pin_28_;
//
output [0:0] top_grid_pin_29_;
//
output [0:0] top_grid_pin_30_;
//
output [0:0] top_grid_pin_31_;
//
output [0:0] ccff_tail;
//
//
// module cbx_1__1_
// (
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_1_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_3_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_5_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_7_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_9_,
output [0:0] bottom_grid_pin_10_,
output [0:0] bottom_grid_pin_11_,
output [0:0] bottom_grid_pin_12_,
output [0:0] bottom_grid_pin_13_,
output [0:0] bottom_grid_pin_14_,
output [0:0] bottom_grid_pin_15_,
output [0:0] ccff_tail,
input CLB_SC_IN,
output CLB_SC_OUT,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign CLB_SC_OUT = CLB_SC_IN;
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
wire [0:3] mux_tree_tapbuf_size10_0_sram; mux_tree_tapbuf_size10
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; mux_top_ipin_3
wire [0:3] mux_tree_tapbuf_size10_1_sram; (
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
wire [0:3] mux_tree_tapbuf_size10_2_sram; .sram(mux_tree_tapbuf_size10_1_sram[0:3]),
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
wire [0:3] mux_tree_tapbuf_size10_3_sram; .out(bottom_grid_pin_3_[0])
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; );
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
//
//
//
//
assign chanx_right_out[0] = chanx_left_in[0];
//
//
//
assign chanx_right_out[1] = chanx_left_in[1];
//
//
//
assign chanx_right_out[2] = chanx_left_in[2];
//
//
//
assign chanx_right_out[3] = chanx_left_in[3];
//
//
//
assign chanx_right_out[4] = chanx_left_in[4];
//
//
//
assign chanx_right_out[5] = chanx_left_in[5];
//
//
//
assign chanx_right_out[6] = chanx_left_in[6];
//
//
//
assign chanx_right_out[7] = chanx_left_in[7];
//
//
//
assign chanx_right_out[8] = chanx_left_in[8];
//
//
//
assign chanx_right_out[9] = chanx_left_in[9];
//
//
//
assign chanx_right_out[10] = chanx_left_in[10];
//
//
//
assign chanx_right_out[11] = chanx_left_in[11];
//
//
//
assign chanx_right_out[12] = chanx_left_in[12];
//
//
//
assign chanx_right_out[13] = chanx_left_in[13];
//
//
//
assign chanx_right_out[14] = chanx_left_in[14];
//
//
//
assign chanx_right_out[15] = chanx_left_in[15];
//
//
//
assign chanx_right_out[16] = chanx_left_in[16];
//
//
//
assign chanx_right_out[17] = chanx_left_in[17];
//
//
//
assign chanx_right_out[18] = chanx_left_in[18];
//
//
//
assign chanx_right_out[19] = chanx_left_in[19];
//
//
//
assign chanx_left_out[0] = chanx_right_in[0];
//
//
//
assign chanx_left_out[1] = chanx_right_in[1];
//
//
//
assign chanx_left_out[2] = chanx_right_in[2];
//
//
//
assign chanx_left_out[3] = chanx_right_in[3];
//
//
//
assign chanx_left_out[4] = chanx_right_in[4];
//
//
//
assign chanx_left_out[5] = chanx_right_in[5];
//
//
//
assign chanx_left_out[6] = chanx_right_in[6];
//
//
//
assign chanx_left_out[7] = chanx_right_in[7];
//
//
//
assign chanx_left_out[8] = chanx_right_in[8];
//
//
//
assign chanx_left_out[9] = chanx_right_in[9];
//
//
//
assign chanx_left_out[10] = chanx_right_in[10];
//
//
//
assign chanx_left_out[11] = chanx_right_in[11];
//
//
//
assign chanx_left_out[12] = chanx_right_in[12];
//
//
//
assign chanx_left_out[13] = chanx_right_in[13];
//
//
//
assign chanx_left_out[14] = chanx_right_in[14];
//
//
//
assign chanx_left_out[15] = chanx_right_in[15];
//
//
//
assign chanx_left_out[16] = chanx_right_in[16];
//
//
//
assign chanx_left_out[17] = chanx_right_in[17];
//
//
//
assign chanx_left_out[18] = chanx_right_in[18];
//
//
//
assign chanx_left_out[19] = chanx_right_in[19];
//
//
//
mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), mux_top_ipin_4
.sram(mux_tree_tapbuf_size10_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.out(top_grid_pin_16_[0])); .sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(top_grid_pin_17_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), mux_top_ipin_7
.sram(mux_tree_tapbuf_size10_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.out(top_grid_pin_20_[0])); .sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_5 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(top_grid_pin_21_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), mux_top_ipin_8
.sram(mux_tree_tapbuf_size10_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.out(top_grid_pin_24_[0])); .sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_9 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(top_grid_pin_25_[0]));
mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), mux_top_ipin_11
.sram(mux_tree_tapbuf_size10_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }),
.out(top_grid_pin_28_[0])); .sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10 mux_bottom_ipin_13 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(top_grid_pin_29_[0]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( mux_tree_tapbuf_size10
.prog_clk(prog_clk[0]), mux_top_ipin_12
.ccff_head(ccff_head[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), .sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( mux_tree_tapbuf_size10
.prog_clk(prog_clk[0]), mux_top_ipin_15
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), .sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_0
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), .ccff_head(ccff_head[0]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_3
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), mem_top_ipin_4
.sram(mux_tree_tapbuf_size8_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_18_[0])); .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_3 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(top_grid_pin_19_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), mem_top_ipin_7
.sram(mux_tree_tapbuf_size8_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_22_[0])); .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_7 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(top_grid_pin_23_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), mem_top_ipin_8
.sram(mux_tree_tapbuf_size8_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_26_[0])); .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_11 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(top_grid_pin_27_[0]));
mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( mux_tree_tapbuf_size10_mem
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), mem_top_ipin_11
.sram(mux_tree_tapbuf_size8_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(top_grid_pin_30_[0])); .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_bottom_ipin_15 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(top_grid_pin_31_[0]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_12
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_top_ipin_15
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); .ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( mux_tree_tapbuf_size8
.prog_clk(prog_clk[0]), mux_top_ipin_1
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), .sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( mux_tree_tapbuf_size8
.prog_clk(prog_clk[0]), mux_top_ipin_2
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), .sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]));
endmodule endmodule
//

718
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v
View File

@ -1,230 +1,508 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module cbx_1__2_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_pin_0_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chanx_left_in;
//
input [0:19] chanx_right_in;
//
input [0:0] ccff_head;
//
output [0:19] chanx_left_out;
//
output [0:19] chanx_right_out;
//
output [0:0] top_grid_pin_0_;
//
output [0:0] ccff_tail;
//
//
// module cbx_1__2_
// (
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] top_grid_pin_0_,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_1_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_3_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_5_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_7_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_9_,
output [0:0] bottom_grid_pin_10_,
output [0:0] bottom_grid_pin_11_,
output [0:0] bottom_grid_pin_12_,
output [0:0] bottom_grid_pin_13_,
output [0:0] bottom_grid_pin_14_,
output [0:0] bottom_grid_pin_15_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] bottom_width_0_height_0__pin_0_,
output [0:0] bottom_width_0_height_0__pin_1_upper,
output [0:0] bottom_width_0_height_0__pin_1_lower,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_bottom_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(top_grid_pin_0_[0])
);
wire [0:3] mux_tree_tapbuf_size10_0_sram; mux_tree_tapbuf_size10
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; mux_top_ipin_0
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
//
//
//
//
assign chanx_right_out[0] = chanx_left_in[0];
//
//
//
assign chanx_right_out[1] = chanx_left_in[1];
//
//
//
assign chanx_right_out[2] = chanx_left_in[2];
//
//
//
assign chanx_right_out[3] = chanx_left_in[3];
//
//
//
assign chanx_right_out[4] = chanx_left_in[4];
//
//
//
assign chanx_right_out[5] = chanx_left_in[5];
//
//
//
assign chanx_right_out[6] = chanx_left_in[6];
//
//
//
assign chanx_right_out[7] = chanx_left_in[7];
//
//
//
assign chanx_right_out[8] = chanx_left_in[8];
//
//
//
assign chanx_right_out[9] = chanx_left_in[9];
//
//
//
assign chanx_right_out[10] = chanx_left_in[10];
//
//
//
assign chanx_right_out[11] = chanx_left_in[11];
//
//
//
assign chanx_right_out[12] = chanx_left_in[12];
//
//
//
assign chanx_right_out[13] = chanx_left_in[13];
//
//
//
assign chanx_right_out[14] = chanx_left_in[14];
//
//
//
assign chanx_right_out[15] = chanx_left_in[15];
//
//
//
assign chanx_right_out[16] = chanx_left_in[16];
//
//
//
assign chanx_right_out[17] = chanx_left_in[17];
//
//
//
assign chanx_right_out[18] = chanx_left_in[18];
//
//
//
assign chanx_right_out[19] = chanx_left_in[19];
//
//
//
assign chanx_left_out[0] = chanx_right_in[0];
//
//
//
assign chanx_left_out[1] = chanx_right_in[1];
//
//
//
assign chanx_left_out[2] = chanx_right_in[2];
//
//
//
assign chanx_left_out[3] = chanx_right_in[3];
//
//
//
assign chanx_left_out[4] = chanx_right_in[4];
//
//
//
assign chanx_left_out[5] = chanx_right_in[5];
//
//
//
assign chanx_left_out[6] = chanx_right_in[6];
//
//
//
assign chanx_left_out[7] = chanx_right_in[7];
//
//
//
assign chanx_left_out[8] = chanx_right_in[8];
//
//
//
assign chanx_left_out[9] = chanx_right_in[9];
//
//
//
assign chanx_left_out[10] = chanx_right_in[10];
//
//
//
assign chanx_left_out[11] = chanx_right_in[11];
//
//
//
assign chanx_left_out[12] = chanx_right_in[12];
//
//
//
assign chanx_left_out[13] = chanx_right_in[13];
//
//
//
assign chanx_left_out[14] = chanx_right_in[14];
//
//
//
assign chanx_left_out[15] = chanx_right_in[15];
//
//
//
assign chanx_left_out[16] = chanx_right_in[16];
//
//
//
assign chanx_left_out[17] = chanx_right_in[17];
//
//
//
assign chanx_left_out[18] = chanx_right_in[18];
//
//
//
assign chanx_left_out[19] = chanx_right_in[19];
//
//
//
mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( mux_tree_tapbuf_size10
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), mux_top_ipin_3
.sram(mux_tree_tapbuf_size10_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.out(top_grid_pin_0_[0])); .sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_bottom_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
endmodule endmodule
//

331
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v
View File

@ -1,249 +1,102 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module cby_0__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_pin_52_,
left_grid_pin_0_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chany_bottom_in;
//
input [0:19] chany_top_in;
//
input [0:0] ccff_head;
//
output [0:19] chany_bottom_out;
//
output [0:19] chany_top_out;
//
output [0:0] right_grid_pin_52_;
//
output [0:0] left_grid_pin_0_;
//
output [0:0] ccff_tail;
//
//
// module cby_0__1_
// (
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] left_grid_pin_0_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] right_width_0_height_0__pin_0_,
output [0:0] right_width_0_height_0__pin_1_upper,
output [0:0] right_width_0_height_0__pin_1_lower
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire ccff_tail_mid;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(left_grid_pin_0_[0])
);
wire [0:3] mux_tree_tapbuf_size10_0_sram; mux_tree_tapbuf_size10_mem
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; mem_right_ipin_0
wire [0:3] mux_tree_tapbuf_size10_1_sram; (
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; .prog_clk(prog_clk[0]),
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; .ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
//
//
//
//
assign chany_top_out[0] = chany_bottom_in[0];
//
//
//
assign chany_top_out[1] = chany_bottom_in[1];
//
//
//
assign chany_top_out[2] = chany_bottom_in[2];
//
//
//
assign chany_top_out[3] = chany_bottom_in[3];
//
//
//
assign chany_top_out[4] = chany_bottom_in[4];
//
//
//
assign chany_top_out[5] = chany_bottom_in[5];
//
//
//
assign chany_top_out[6] = chany_bottom_in[6];
//
//
//
assign chany_top_out[7] = chany_bottom_in[7];
//
//
//
assign chany_top_out[8] = chany_bottom_in[8];
//
//
//
assign chany_top_out[9] = chany_bottom_in[9];
//
//
//
assign chany_top_out[10] = chany_bottom_in[10];
//
//
//
assign chany_top_out[11] = chany_bottom_in[11];
//
//
//
assign chany_top_out[12] = chany_bottom_in[12];
//
//
//
assign chany_top_out[13] = chany_bottom_in[13];
//
//
//
assign chany_top_out[14] = chany_bottom_in[14];
//
//
//
assign chany_top_out[15] = chany_bottom_in[15];
//
//
//
assign chany_top_out[16] = chany_bottom_in[16];
//
//
//
assign chany_top_out[17] = chany_bottom_in[17];
//
//
//
assign chany_top_out[18] = chany_bottom_in[18];
//
//
//
assign chany_top_out[19] = chany_bottom_in[19];
//
//
//
assign chany_bottom_out[0] = chany_top_in[0];
//
//
//
assign chany_bottom_out[1] = chany_top_in[1];
//
//
//
assign chany_bottom_out[2] = chany_top_in[2];
//
//
//
assign chany_bottom_out[3] = chany_top_in[3];
//
//
//
assign chany_bottom_out[4] = chany_top_in[4];
//
//
//
assign chany_bottom_out[5] = chany_top_in[5];
//
//
//
assign chany_bottom_out[6] = chany_top_in[6];
//
//
//
assign chany_bottom_out[7] = chany_top_in[7];
//
//
//
assign chany_bottom_out[8] = chany_top_in[8];
//
//
//
assign chany_bottom_out[9] = chany_top_in[9];
//
//
//
assign chany_bottom_out[10] = chany_top_in[10];
//
//
//
assign chany_bottom_out[11] = chany_top_in[11];
//
//
//
assign chany_bottom_out[12] = chany_top_in[12];
//
//
//
assign chany_bottom_out[13] = chany_top_in[13];
//
//
//
assign chany_bottom_out[14] = chany_top_in[14];
//
//
//
assign chany_bottom_out[15] = chany_top_in[15];
//
//
//
assign chany_bottom_out[16] = chany_top_in[16];
//
//
//
assign chany_bottom_out[17] = chany_top_in[17];
//
//
//
assign chany_bottom_out[18] = chany_top_in[18];
//
//
//
assign chany_bottom_out[19] = chany_top_in[19];
//
//
//
mux_tree_tapbuf_size10 mux_left_ipin_0 ( logical_tile_io_mode_io_
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), logical_tile_io_mode_io__0
.sram(mux_tree_tapbuf_size10_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(right_grid_pin_52_[0])); .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
mux_tree_tapbuf_size10 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(left_grid_pin_0_[0]));
mux_tree_tapbuf_size10_mem mem_left_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]));
endmodule endmodule
//

905
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v
View File

@ -1,534 +1,455 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module cby_1__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_pin_52_,
left_grid_pin_0_,
left_grid_pin_1_,
left_grid_pin_2_,
left_grid_pin_3_,
left_grid_pin_4_,
left_grid_pin_5_,
left_grid_pin_6_,
left_grid_pin_7_,
left_grid_pin_8_,
left_grid_pin_9_,
left_grid_pin_10_,
left_grid_pin_11_,
left_grid_pin_12_,
left_grid_pin_13_,
left_grid_pin_14_,
left_grid_pin_15_,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chany_bottom_in;
//
input [0:19] chany_top_in;
//
input [0:0] ccff_head;
//
output [0:19] chany_bottom_out;
//
output [0:19] chany_top_out;
//
output [0:0] right_grid_pin_52_;
//
output [0:0] left_grid_pin_0_;
//
output [0:0] left_grid_pin_1_;
//
output [0:0] left_grid_pin_2_;
//
output [0:0] left_grid_pin_3_;
//
output [0:0] left_grid_pin_4_;
//
output [0:0] left_grid_pin_5_;
//
output [0:0] left_grid_pin_6_;
//
output [0:0] left_grid_pin_7_;
//
output [0:0] left_grid_pin_8_;
//
output [0:0] left_grid_pin_9_;
//
output [0:0] left_grid_pin_10_;
//
output [0:0] left_grid_pin_11_;
//
output [0:0] left_grid_pin_12_;
//
output [0:0] left_grid_pin_13_;
//
output [0:0] left_grid_pin_14_;
//
output [0:0] left_grid_pin_15_;
//
output [0:0] ccff_tail;
//
//
// module cby_1__1_
// (
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] left_grid_pin_16_,
output [0:0] left_grid_pin_17_,
output [0:0] left_grid_pin_18_,
output [0:0] left_grid_pin_19_,
output [0:0] left_grid_pin_20_,
output [0:0] left_grid_pin_21_,
output [0:0] left_grid_pin_22_,
output [0:0] left_grid_pin_23_,
output [0:0] left_grid_pin_24_,
output [0:0] left_grid_pin_25_,
output [0:0] left_grid_pin_26_,
output [0:0] left_grid_pin_27_,
output [0:0] left_grid_pin_28_,
output [0:0] left_grid_pin_29_,
output [0:0] left_grid_pin_30_,
output [0:0] left_grid_pin_31_,
output [0:0] ccff_tail
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
wire [0:3] mux_tree_tapbuf_size10_0_sram; mux_tree_tapbuf_size10
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; mux_right_ipin_3
wire [0:3] mux_tree_tapbuf_size10_1_sram; (
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
wire [0:3] mux_tree_tapbuf_size10_2_sram; .sram(mux_tree_tapbuf_size10_1_sram[0:3]),
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
wire [0:3] mux_tree_tapbuf_size10_3_sram; .out(left_grid_pin_19_[0])
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; );
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
//
//
//
//
assign chany_top_out[0] = chany_bottom_in[0];
//
//
//
assign chany_top_out[1] = chany_bottom_in[1];
//
//
//
assign chany_top_out[2] = chany_bottom_in[2];
//
//
//
assign chany_top_out[3] = chany_bottom_in[3];
//
//
//
assign chany_top_out[4] = chany_bottom_in[4];
//
//
//
assign chany_top_out[5] = chany_bottom_in[5];
//
//
//
assign chany_top_out[6] = chany_bottom_in[6];
//
//
//
assign chany_top_out[7] = chany_bottom_in[7];
//
//
//
assign chany_top_out[8] = chany_bottom_in[8];
//
//
//
assign chany_top_out[9] = chany_bottom_in[9];
//
//
//
assign chany_top_out[10] = chany_bottom_in[10];
//
//
//
assign chany_top_out[11] = chany_bottom_in[11];
//
//
//
assign chany_top_out[12] = chany_bottom_in[12];
//
//
//
assign chany_top_out[13] = chany_bottom_in[13];
//
//
//
assign chany_top_out[14] = chany_bottom_in[14];
//
//
//
assign chany_top_out[15] = chany_bottom_in[15];
//
//
//
assign chany_top_out[16] = chany_bottom_in[16];
//
//
//
assign chany_top_out[17] = chany_bottom_in[17];
//
//
//
assign chany_top_out[18] = chany_bottom_in[18];
//
//
//
assign chany_top_out[19] = chany_bottom_in[19];
//
//
//
assign chany_bottom_out[0] = chany_top_in[0];
//
//
//
assign chany_bottom_out[1] = chany_top_in[1];
//
//
//
assign chany_bottom_out[2] = chany_top_in[2];
//
//
//
assign chany_bottom_out[3] = chany_top_in[3];
//
//
//
assign chany_bottom_out[4] = chany_top_in[4];
//
//
//
assign chany_bottom_out[5] = chany_top_in[5];
//
//
//
assign chany_bottom_out[6] = chany_top_in[6];
//
//
//
assign chany_bottom_out[7] = chany_top_in[7];
//
//
//
assign chany_bottom_out[8] = chany_top_in[8];
//
//
//
assign chany_bottom_out[9] = chany_top_in[9];
//
//
//
assign chany_bottom_out[10] = chany_top_in[10];
//
//
//
assign chany_bottom_out[11] = chany_top_in[11];
//
//
//
assign chany_bottom_out[12] = chany_top_in[12];
//
//
//
assign chany_bottom_out[13] = chany_top_in[13];
//
//
//
assign chany_bottom_out[14] = chany_top_in[14];
//
//
//
assign chany_bottom_out[15] = chany_top_in[15];
//
//
//
assign chany_bottom_out[16] = chany_top_in[16];
//
//
//
assign chany_bottom_out[17] = chany_top_in[17];
//
//
//
assign chany_bottom_out[18] = chany_top_in[18];
//
//
//
assign chany_bottom_out[19] = chany_top_in[19];
//
//
//
mux_tree_tapbuf_size10 mux_left_ipin_0 ( mux_tree_tapbuf_size10
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), mux_right_ipin_4
.sram(mux_tree_tapbuf_size10_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.out(right_grid_pin_52_[0])); .sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(left_grid_pin_0_[0]));
mux_tree_tapbuf_size10 mux_right_ipin_1 ( mux_tree_tapbuf_size10
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18]}), mux_right_ipin_7
.sram(mux_tree_tapbuf_size10_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.out(left_grid_pin_1_[0])); .sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10 mux_right_ipin_4 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(left_grid_pin_4_[0]));
mux_tree_tapbuf_size10 mux_right_ipin_5 ( mux_tree_tapbuf_size10
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), mux_right_ipin_8
.sram(mux_tree_tapbuf_size10_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.out(left_grid_pin_5_[0])); .sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10 mux_right_ipin_8 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(left_grid_pin_8_[0]));
mux_tree_tapbuf_size10 mux_right_ipin_9 ( mux_tree_tapbuf_size10
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[14], chany_top_in[14]}), mux_right_ipin_11
.sram(mux_tree_tapbuf_size10_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }),
.out(left_grid_pin_9_[0])); .sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10 mux_right_ipin_12 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(left_grid_pin_12_[0]));
mux_tree_tapbuf_size10 mux_right_ipin_13 ( mux_tree_tapbuf_size10
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[18], chany_top_in[18]}), mux_right_ipin_12
.sram(mux_tree_tapbuf_size10_8_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.out(left_grid_pin_13_[0])); .sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10_mem mem_left_ipin_0 (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( mux_tree_tapbuf_size10
.prog_clk(prog_clk[0]), mux_right_ipin_15
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), .sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_4 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_right_ipin_0
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), .ccff_head(ccff_head[0]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_right_ipin_3
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_12 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_right_ipin_4
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_right_ipin_2 ( mux_tree_tapbuf_size10_mem
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), mem_right_ipin_7
.sram(mux_tree_tapbuf_size8_0_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(left_grid_pin_2_[0])); .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_right_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(left_grid_pin_3_[0]));
mux_tree_tapbuf_size8 mux_right_ipin_6 ( mux_tree_tapbuf_size10_mem
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), mem_right_ipin_8
.sram(mux_tree_tapbuf_size8_2_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(left_grid_pin_6_[0])); .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_right_ipin_7 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(left_grid_pin_7_[0]));
mux_tree_tapbuf_size8 mux_right_ipin_10 ( mux_tree_tapbuf_size10_mem
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), mem_right_ipin_11
.sram(mux_tree_tapbuf_size8_4_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(left_grid_pin_10_[0])); .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_right_ipin_11 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(left_grid_pin_11_[0]));
mux_tree_tapbuf_size8 mux_right_ipin_14 ( mux_tree_tapbuf_size10_mem
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), mem_right_ipin_12
.sram(mux_tree_tapbuf_size8_6_sram[0:3]), (
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), .prog_clk(prog_clk[0]),
.out(left_grid_pin_14_[0])); .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8 mux_right_ipin_15 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(left_grid_pin_15_[0]));
mux_tree_tapbuf_size8_mem mem_right_ipin_2 ( mux_tree_tapbuf_size10_mem
.prog_clk(prog_clk[0]), mem_right_ipin_15
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); .ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem mem_right_ipin_3 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_right_ipin_6 ( mux_tree_tapbuf_size8
.prog_clk(prog_clk[0]), mux_right_ipin_1
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), .sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8_mem mem_right_ipin_7 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_right_ipin_10 ( mux_tree_tapbuf_size8
.prog_clk(prog_clk[0]), mux_right_ipin_2
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), .sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8_mem mem_right_ipin_11 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( mux_tree_tapbuf_size8
.prog_clk(prog_clk[0]), mux_right_ipin_5
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), .sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem mem_right_ipin_15 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]));
endmodule endmodule
//

502
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v Normal file
View File

@ -0,0 +1,502 @@
module cby_2__1_
(
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] right_grid_pin_0_,
output [0:0] left_grid_pin_16_,
output [0:0] left_grid_pin_17_,
output [0:0] left_grid_pin_18_,
output [0:0] left_grid_pin_19_,
output [0:0] left_grid_pin_20_,
output [0:0] left_grid_pin_21_,
output [0:0] left_grid_pin_22_,
output [0:0] left_grid_pin_23_,
output [0:0] left_grid_pin_24_,
output [0:0] left_grid_pin_25_,
output [0:0] left_grid_pin_26_,
output [0:0] left_grid_pin_27_,
output [0:0] left_grid_pin_28_,
output [0:0] left_grid_pin_29_,
output [0:0] left_grid_pin_30_,
output [0:0] left_grid_pin_31_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] left_width_0_height_0__pin_0_,
output [0:0] left_width_0_height_0__pin_1_upper,
output [0:0] left_width_0_height_0__pin_1_lower
);
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
mux_tree_tapbuf_size10
mux_left_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(right_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_left_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
endmodule

890
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v
View File

@ -1,456 +1,522 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module sb_0__0_(prog_clk,
chany_top_in,
top_left_grid_pin_1_,
chanx_right_in,
right_top_grid_pin_42_,
right_top_grid_pin_43_,
right_top_grid_pin_44_,
right_top_grid_pin_45_,
right_top_grid_pin_46_,
right_top_grid_pin_47_,
right_top_grid_pin_48_,
right_top_grid_pin_49_,
right_bottom_grid_pin_1_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chany_top_in;
//
input [0:0] top_left_grid_pin_1_;
//
input [0:19] chanx_right_in;
//
input [0:0] right_top_grid_pin_42_;
//
input [0:0] right_top_grid_pin_43_;
//
input [0:0] right_top_grid_pin_44_;
//
input [0:0] right_top_grid_pin_45_;
//
input [0:0] right_top_grid_pin_46_;
//
input [0:0] right_top_grid_pin_47_;
//
input [0:0] right_top_grid_pin_48_;
//
input [0:0] right_top_grid_pin_49_;
//
input [0:0] right_bottom_grid_pin_1_;
//
input [0:0] ccff_head;
//
output [0:19] chany_top_out;
//
output [0:19] chanx_right_out;
//
output [0:0] ccff_tail;
//
//
// module sb_0__0_
// (
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_1_,
input [0:19] chanx_right_in,
input [0:0] right_bottom_grid_pin_1_,
input [0:0] right_bottom_grid_pin_3_,
input [0:0] right_bottom_grid_pin_5_,
input [0:0] right_bottom_grid_pin_7_,
input [0:0] right_bottom_grid_pin_9_,
input [0:0] right_bottom_grid_pin_11_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_right_out,
output [0:0] ccff_tail
);
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
assign chanx_right_out[10] = chany_top_in[9];
assign chanx_right_out[11] = chany_top_in[10];
assign chanx_right_out[18] = chany_top_in[17];
assign chanx_right_out[19] = chany_top_in[18];
assign chany_top_out[19] = chanx_right_in[0];
assign chany_top_out[1] = chanx_right_in[2];
assign chany_top_out[3] = chanx_right_in[4];
assign chany_top_out[5] = chanx_right_in[6];
assign chany_top_out[6] = chanx_right_in[7];
assign chany_top_out[7] = chanx_right_in[8];
assign chany_top_out[8] = chanx_right_in[9];
assign chany_top_out[9] = chanx_right_in[10];
assign chany_top_out[10] = chanx_right_in[11];
assign chany_top_out[11] = chanx_right_in[12];
assign chany_top_out[13] = chanx_right_in[14];
assign chany_top_out[14] = chanx_right_in[15];
assign chany_top_out[15] = chanx_right_in[16];
assign chany_top_out[16] = chanx_right_in[17];
assign chany_top_out[17] = chanx_right_in[18];
assign chany_top_out[18] = chanx_right_in[19];
mux_tree_tapbuf_size2
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[0])
);
wire [0:1] mux_tree_tapbuf_size2_0_sram; mux_tree_tapbuf_size2
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; mux_top_track_4
wire [0:1] mux_tree_tapbuf_size2_10_sram; (
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; .in({ top_left_grid_pin_1_[0], chanx_right_in[3] }),
wire [0:1] mux_tree_tapbuf_size2_11_sram; .sram(mux_tree_tapbuf_size2_1_sram[0:1]),
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
wire [0:1] mux_tree_tapbuf_size2_1_sram; .out(chany_top_out[2])
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; );
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
//
//
//
//
assign chanx_right_out[14] = chany_top_in[13];
//
//
//
assign chanx_right_out[15] = chany_top_in[14];
//
//
//
assign chanx_right_out[16] = chany_top_in[15];
//
//
//
assign chanx_right_out[17] = chany_top_in[16];
//
//
//
assign chanx_right_out[18] = chany_top_in[17];
//
//
//
assign chanx_right_out[19] = chany_top_in[18];
//
//
//
assign chany_top_out[19] = chanx_right_in[0];
//
//
//
assign chany_top_out[1] = chanx_right_in[2];
//
//
//
assign chany_top_out[3] = chanx_right_in[4];
//
//
//
assign chany_top_out[5] = chanx_right_in[6];
//
//
//
assign chany_top_out[6] = chanx_right_in[7];
//
//
//
assign chany_top_out[7] = chanx_right_in[8];
//
//
//
assign chany_top_out[8] = chanx_right_in[9];
//
//
//
assign chany_top_out[9] = chanx_right_in[10];
//
//
//
assign chany_top_out[10] = chanx_right_in[11];
//
//
//
assign chany_top_out[11] = chanx_right_in[12];
//
//
//
assign chany_top_out[13] = chanx_right_in[14];
//
//
//
assign chany_top_out[14] = chanx_right_in[15];
//
//
//
assign chany_top_out[15] = chanx_right_in[16];
//
//
//
assign chany_top_out[16] = chanx_right_in[17];
//
//
//
assign chany_top_out[17] = chanx_right_in[18];
//
//
//
assign chany_top_out[18] = chanx_right_in[19];
//
//
//
mux_tree_tapbuf_size2 mux_top_track_0 ( mux_tree_tapbuf_size2
.in({top_left_grid_pin_1_[0], chanx_right_in[1]}), mux_top_track_8
.sram(mux_tree_tapbuf_size2_0_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), .in({ top_left_grid_pin_1_[0], chanx_right_in[5] }),
.out(chany_top_out[0])); .sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_pin_1_[0], chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size2 mux_top_track_8 ( mux_tree_tapbuf_size2
.in({top_left_grid_pin_1_[0], chanx_right_in[5]}), mux_top_track_24
.sram(mux_tree_tapbuf_size2_2_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), .in({ top_left_grid_pin_1_[0], chanx_right_in[13] }),
.out(chany_top_out[4])); .sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size2 mux_top_track_24 (
.in({top_left_grid_pin_1_[0], chanx_right_in[13]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[12]));
mux_tree_tapbuf_size2 mux_right_track_10 ( mux_tree_tapbuf_size2
.in({chany_top_in[4], right_top_grid_pin_43_[0]}), mux_right_track_8
.sram(mux_tree_tapbuf_size2_4_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), .in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }),
.out(chanx_right_out[5])); .sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size2 mux_right_track_12 (
.in({chany_top_in[5], right_top_grid_pin_44_[0]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size2 mux_right_track_14 ( mux_tree_tapbuf_size2
.in({chany_top_in[6], right_top_grid_pin_45_[0]}), mux_right_track_10
.sram(mux_tree_tapbuf_size2_6_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), .in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }),
.out(chanx_right_out[7])); .sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({chany_top_in[7], right_top_grid_pin_46_[0]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2 mux_right_track_18 ( mux_tree_tapbuf_size2
.in({chany_top_in[8], right_top_grid_pin_47_[0]}), mux_right_track_12
.sram(mux_tree_tapbuf_size2_8_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), .in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }),
.out(chanx_right_out[9])); .sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2 mux_right_track_20 (
.in({chany_top_in[9], right_top_grid_pin_48_[0]}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_right_out[10]));
mux_tree_tapbuf_size2 mux_right_track_22 ( mux_tree_tapbuf_size2
.in({chany_top_in[10], right_top_grid_pin_49_[0]}), mux_right_track_14
.sram(mux_tree_tapbuf_size2_10_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), .in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }),
.out(chanx_right_out[11])); .sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2 mux_right_track_26 (
.in({chany_top_in[12], right_top_grid_pin_43_[0]}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_right_out[13]));
mux_tree_tapbuf_size2_mem mem_top_track_0 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_16
.ccff_head(ccff_head[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), .sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2_mem mem_top_track_4 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_8 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_18
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), .sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2_mem mem_top_track_24 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_24
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), .sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size2_mem mem_right_track_12 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_14 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_26
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), .sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_18 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_28
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), .in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), .sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2_mem mem_right_track_20 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_22 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_30
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), .in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), .sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2_mem mem_right_track_26 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]));
mux_tree_tapbuf_size6 mux_right_track_0 ( mux_tree_tapbuf_size2
.in({chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), mux_right_track_32
.sram(mux_tree_tapbuf_size6_0_sram[0:2]), (
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), .in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }),
.out(chanx_right_out[0])); .sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size6 mux_right_track_4 (
.in({chany_top_in[1], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size6_mem mem_right_track_0 ( mux_tree_tapbuf_size2
.prog_clk(prog_clk[0]), mux_right_track_34
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), .sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size6_mem mem_right_track_4 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
mux_tree_tapbuf_size5 mux_right_track_2 ( mux_tree_tapbuf_size2_mem
.in({chany_top_in[0], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), mem_top_track_0
.sram(mux_tree_tapbuf_size5_0_sram[0:2]), (
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), .prog_clk(prog_clk[0]),
.out(chanx_right_out[1])); .ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
);
mux_tree_tapbuf_size5 mux_right_track_6 (
.in({chany_top_in[2], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size5_mem mem_right_track_2 ( mux_tree_tapbuf_size2_mem
.prog_clk(prog_clk[0]), mem_top_track_4
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
);
mux_tree_tapbuf_size5_mem mem_right_track_6 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_right_track_8 ( mux_tree_tapbuf_size2_mem
.in({chany_top_in[3], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), mem_top_track_8
.sram(mux_tree_tapbuf_size3_0_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), .prog_clk(prog_clk[0]),
.out(chanx_right_out[4])); .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
);
mux_tree_tapbuf_size3 mux_right_track_24 (
.in({chany_top_in[11], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[12]));
mux_tree_tapbuf_size3_mem mem_right_track_8 ( mux_tree_tapbuf_size2_mem
.prog_clk(prog_clk[0]), mem_top_track_24
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
);
mux_tree_tapbuf_size4
mux_right_track_0
(
.in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size4
mux_right_track_2
(
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size4
mux_right_track_4
(
.in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size4
mux_right_track_6
(
.in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size4_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])
);
mux_tree_tapbuf_size3_mem mem_right_track_24 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
endmodule endmodule
//

1376
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v
View File

File diff suppressed because it is too large Load Diff

887
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v
View File

@ -1,312 +1,623 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module sb_0__2_(prog_clk,
chanx_right_in,
right_top_grid_pin_1_,
chany_bottom_in,
bottom_left_grid_pin_1_,
ccff_head,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:19] chanx_right_in;
//
input [0:0] right_top_grid_pin_1_;
//
input [0:19] chany_bottom_in;
//
input [0:0] bottom_left_grid_pin_1_;
//
input [0:0] ccff_head;
//
output [0:19] chanx_right_out;
//
output [0:19] chany_bottom_out;
//
output [0:0] ccff_tail;
//
//
// module sb_0__2_
// (
input [0:0] prog_clk,
input [0:19] chanx_right_in,
input [0:0] right_top_grid_pin_1_,
input [0:0] right_bottom_grid_pin_34_,
input [0:0] right_bottom_grid_pin_35_,
input [0:0] right_bottom_grid_pin_36_,
input [0:0] right_bottom_grid_pin_37_,
input [0:0] right_bottom_grid_pin_38_,
input [0:0] right_bottom_grid_pin_39_,
input [0:0] right_bottom_grid_pin_40_,
input [0:0] right_bottom_grid_pin_41_,
input [0:19] chany_bottom_in,
input [0:0] bottom_left_grid_pin_1_,
input [0:0] ccff_head,
output [0:19] chanx_right_out,
output [0:19] chany_bottom_out,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chany_bottom_out[16] = chanx_right_in[2];
assign chany_bottom_out[15] = chanx_right_in[3];
assign chany_bottom_out[14] = chanx_right_in[4];
assign chany_bottom_out[13] = chanx_right_in[5];
assign chany_bottom_out[11] = chanx_right_in[7];
assign chany_bottom_out[10] = chanx_right_in[8];
assign chany_bottom_out[9] = chanx_right_in[9];
assign chany_bottom_out[8] = chanx_right_in[10];
assign chany_bottom_out[7] = chanx_right_in[11];
assign chany_bottom_out[6] = chanx_right_in[12];
assign chany_bottom_out[5] = chanx_right_in[13];
assign chany_bottom_out[3] = chanx_right_in[15];
assign chany_bottom_out[1] = chanx_right_in[17];
assign chany_bottom_out[19] = chanx_right_in[19];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.out(chanx_right_out[0])
);
wire [0:1] mux_tree_tapbuf_size2_0_sram; mux_tree_tapbuf_size6
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; mux_right_track_4
wire [0:1] mux_tree_tapbuf_size2_1_sram; (
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
wire [0:1] mux_tree_tapbuf_size2_2_sram; .sram(mux_tree_tapbuf_size6_1_sram[0:2]),
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
wire [0:1] mux_tree_tapbuf_size2_3_sram; .out(chanx_right_out[2])
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; );
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
//
//
//
//
assign chany_bottom_out[18] = chanx_right_in[0];
//
//
//
assign chany_bottom_out[17] = chanx_right_in[1];
//
//
//
assign chany_bottom_out[16] = chanx_right_in[2];
//
//
//
assign chany_bottom_out[15] = chanx_right_in[3];
//
//
//
assign chany_bottom_out[14] = chanx_right_in[4];
//
//
//
assign chany_bottom_out[13] = chanx_right_in[5];
//
//
//
assign chany_bottom_out[11] = chanx_right_in[7];
//
//
//
assign chany_bottom_out[10] = chanx_right_in[8];
//
//
//
assign chany_bottom_out[9] = chanx_right_in[9];
//
//
//
assign chany_bottom_out[8] = chanx_right_in[10];
//
//
//
assign chany_bottom_out[7] = chanx_right_in[11];
//
//
//
assign chany_bottom_out[6] = chanx_right_in[12];
//
//
//
assign chany_bottom_out[5] = chanx_right_in[13];
//
//
//
assign chany_bottom_out[3] = chanx_right_in[15];
//
//
//
assign chany_bottom_out[1] = chanx_right_in[17];
//
//
//
assign chany_bottom_out[19] = chanx_right_in[19];
//
//
//
assign chanx_right_out[18] = chany_bottom_in[0];
//
//
//
assign chanx_right_out[17] = chany_bottom_in[1];
//
//
//
assign chanx_right_out[16] = chany_bottom_in[2];
//
//
//
assign chanx_right_out[15] = chany_bottom_in[3];
//
//
//
assign chanx_right_out[14] = chany_bottom_in[4];
//
//
//
assign chanx_right_out[13] = chany_bottom_in[5];
//
//
//
assign chanx_right_out[11] = chany_bottom_in[7];
//
//
//
assign chanx_right_out[10] = chany_bottom_in[8];
//
//
//
assign chanx_right_out[9] = chany_bottom_in[9];
//
//
//
assign chanx_right_out[8] = chany_bottom_in[10];
//
//
//
assign chanx_right_out[7] = chany_bottom_in[11];
//
//
//
assign chanx_right_out[6] = chany_bottom_in[12];
//
//
//
assign chanx_right_out[5] = chany_bottom_in[13];
//
//
//
assign chanx_right_out[3] = chany_bottom_in[15];
//
//
//
assign chanx_right_out[1] = chany_bottom_in[17];
//
//
//
assign chanx_right_out[19] = chany_bottom_in[19];
//
//
//
mux_tree_tapbuf_size2 mux_right_track_0 ( mux_tree_tapbuf_size6_mem
.in({right_top_grid_pin_1_[0], chany_bottom_in[18]}), mem_right_track_0
.sram(mux_tree_tapbuf_size2_0_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), .prog_clk(prog_clk[0]),
.out(chanx_right_out[0])); .ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
);
mux_tree_tapbuf_size2 mux_right_track_4 (
.in({right_top_grid_pin_1_[0], chany_bottom_in[16]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size2 mux_right_track_8 ( mux_tree_tapbuf_size6_mem
.in({right_top_grid_pin_1_[0], chany_bottom_in[14]}), mem_right_track_4
.sram(mux_tree_tapbuf_size2_2_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), .prog_clk(prog_clk[0]),
.out(chanx_right_out[4])); .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
);
mux_tree_tapbuf_size2 mux_right_track_24 (
.in({right_top_grid_pin_1_[0], chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_right_out[12]));
mux_tree_tapbuf_size2 mux_bottom_track_1 ( mux_tree_tapbuf_size5
.in({chanx_right_in[18], bottom_left_grid_pin_1_[0]}), mux_right_track_2
.sram(mux_tree_tapbuf_size2_4_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
.out(chany_bottom_out[0])); .sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size2 mux_bottom_track_5 (
.in({chanx_right_in[16], bottom_left_grid_pin_1_[0]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size2 mux_bottom_track_9 ( mux_tree_tapbuf_size5
.in({chanx_right_in[14], bottom_left_grid_pin_1_[0]}), mux_right_track_6
.sram(mux_tree_tapbuf_size2_6_sram[0:1]), (
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }),
.out(chany_bottom_out[4])); .sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size2 mux_bottom_track_25 (
.in({chanx_right_in[6], bottom_left_grid_pin_1_[0]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_bottom_out[12]));
mux_tree_tapbuf_size2_mem mem_right_track_0 ( mux_tree_tapbuf_size5_mem
.prog_clk(prog_clk[0]), mem_right_track_2
.ccff_head(ccff_head[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
);
mux_tree_tapbuf_size2_mem mem_right_track_4 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_8 ( mux_tree_tapbuf_size5_mem
.prog_clk(prog_clk[0]), mem_right_track_6
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .prog_clk(prog_clk[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
);
mux_tree_tapbuf_size2_mem mem_right_track_24 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_1 ( mux_tree_tapbuf_size3
.prog_clk(prog_clk[0]), mux_right_track_8
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), .sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_9 ( mux_tree_tapbuf_size3
.prog_clk(prog_clk[0]), mux_right_track_24
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), (
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), .sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2
mux_bottom_track_1
(
.in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size2
mux_bottom_track_5
(
.in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_25
(
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])
);
mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
endmodule endmodule
//

1511
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v
View File

File diff suppressed because it is too large Load Diff

1461
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v
View File

File diff suppressed because it is too large Load Diff

1481
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v
View File

File diff suppressed because it is too large Load Diff

1426
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v
View File

File diff suppressed because it is too large Load Diff

1436
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v
View File

File diff suppressed because it is too large Load Diff

1300
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v
View File

File diff suppressed because it is too large Load Diff

63
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v Normal file
View File

@ -0,0 +1,63 @@
`timescale 1ns/1ps
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule
//
//
//
//
module EMBEDDED_IO (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR //
);
assign FPGA_IN = SOC_IN;
assign SOC_OUT = FPGA_OUT;
assign SOC_DIR = FPGA_DIR;
endmodule
//
//
//
module GPIN (
inout A, //
output Y //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule
//
//
//
module GPOUT (
inout Y, //
input A //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule

629
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v
View File

@ -130,6 +130,226 @@ endmodule
//
module mux_tree_tapbuf_size4_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
endmodule
//
//
module mux_tree_tapbuf_size7_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
endmodule
//
//
module mux_tree_tapbuf_size11_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
endmodule
//
//
module mux_tree_tapbuf_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
endmodule
//
// //
module mux_tree_tapbuf_size6_mem(prog_clk, module mux_tree_tapbuf_size6_mem(prog_clk,
ccff_head, ccff_head,
@ -240,281 +460,6 @@ endmodule
//
module mux_tree_tapbuf_size14_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
endmodule
//
//
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
endmodule
//
//
module mux_tree_tapbuf_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
endmodule
//
//
module mux_tree_tapbuf_size7_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
endmodule
//
//
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
endmodule
//
// //
module mux_tree_tapbuf_size12_mem(prog_clk, module mux_tree_tapbuf_size12_mem(prog_clk,
ccff_head, ccff_head,
@ -644,7 +589,7 @@ endmodule
// //
module mux_tree_tapbuf_size4_mem(prog_clk, module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head, ccff_head,
ccff_tail, ccff_tail,
mem_out, mem_out,
@ -656,9 +601,9 @@ input [0:0] ccff_head;
// //
output [0:0] ccff_tail; output [0:0] ccff_tail;
// //
output [0:2] mem_out; output [0:1] mem_out;
// //
output [0:2] mem_outb; output [0:1] mem_outb;
// //
// //
@ -672,7 +617,56 @@ output [0:2] mem_outb;
// //
// //
// //
assign ccff_tail[0] = mem_out[2]; assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
endmodule
//
//
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
// //
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
@ -693,6 +687,73 @@ output [0:2] mem_outb;
.Q(mem_out[2]), .Q(mem_out[2]),
.Q_N(mem_outb[2])); .Q_N(mem_outb[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
endmodule
//
//
module mux_tree_tapbuf_size14_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
endmodule endmodule
// //
@ -887,11 +948,11 @@ endmodule
// //
module GPIO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk,
ccff_head, ccff_head,
ccff_tail, ccff_tail,
mem_out, mem_out,
mem_outb); mem_outb);
// //
input [0:0] prog_clk; input [0:0] prog_clk;
// //

1050
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v
View File

File diff suppressed because it is too large Load Diff

472
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v
View File

@ -15,12 +15,11 @@ wire [0:0] Test_en;
wire [0:0] clk; wire [0:0] clk;
// //
wire [0:7] gfpga_pad_GPIO_Y;
wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN;
wire [0:7] gfpga_pad_GPIO_A; wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT;
wire [0:7] gfpga_pad_GPIO_IE; wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR;
wire [0:7] gfpga_pad_GPIO_OE;
reg [0:0] config_done; reg [0:0] config_done;
wire [0:0] prog_clock; wire [0:0] prog_clock;
@ -85,7 +84,7 @@ initial
end end
always wait(~greset) always wait(~greset)
begin begin
#0.4159859717 op_clock_reg[0] = ~op_clock_reg[0]; #0.5203860402 op_clock_reg[0] = ~op_clock_reg[0];
end end
// //
@ -116,8 +115,8 @@ initial
begin begin
greset[0] = 1'b1; greset[0] = 1'b1;
wait(config_done) wait(config_done)
#0.8319719434 greset[0] = 1'b1; #1.04077208 greset[0] = 1'b1;
#1.663943887 greset[0] = 1'b0; #2.081544161 greset[0] = 1'b0;
end end
// //
@ -139,27 +138,57 @@ initial
.prog_clk(prog_clk[0]), .prog_clk(prog_clk[0]),
.Test_en(Test_en[0]), .Test_en(Test_en[0]),
.clk(clk[0]), .clk(clk[0]),
.gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]),
.gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]),
.gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]),
.gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]),
.ccff_head(ccff_head[0]), .ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0])); .ccff_tail(ccff_tail[0]));
// //
// //
assign gfpga_pad_GPIO_Y[4] = a[0]; assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a[0];
//
assign gfpga_pad_GPIO_Y[6] = b[0];
//
assign out:c_fpga[0] = gfpga_pad_GPIO_Y[5];
// //
assign gfpga_pad_GPIO_Y[0] = 1'b0; assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b[0];
assign gfpga_pad_GPIO_Y[1] = 1'b0;
assign gfpga_pad_GPIO_Y[2] = 1'b0; //
assign gfpga_pad_GPIO_Y[3] = 1'b0; assign out:c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9];
assign gfpga_pad_GPIO_Y[7] = 1'b0;
//
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0;
`ifdef AUTOCHECKED_SIMULATION `ifdef AUTOCHECKED_SIMULATION
// //
@ -206,17 +235,10 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -231,9 +253,8 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -245,6 +266,7 @@ initial
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -319,80 +341,6 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -419,30 +367,15 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -808,22 +741,18 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -884,10 +813,10 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -1086,6 +1015,47 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -1188,6 +1158,7 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -1240,32 +1211,8 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -2016,10 +1963,6 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -2045,6 +1988,38 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -2138,6 +2113,67 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1); prog_cycle_task(1'b1);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
@ -2195,6 +2231,96 @@ initial
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0); prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
@(negedge prog_clock[0]); @(negedge prog_clock[0]);
config_done[0] <= 1'b1; config_done[0] <= 1'b1;
end end
@ -2260,7 +2386,7 @@ initial begin
$timeformat(-9, 2, "ns", 20); $timeformat(-9, 2, "ns", 20);
$display("Simulation start"); $display("Simulation start");
// //
#20121 #21092
if(nb_error == 0) begin if(nb_error == 0) begin
$display("Simulation Succeed"); $display("Simulation Succeed");
end else begin end else begin

4
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v
View File

@ -53,7 +53,7 @@ module top_top_formal_verification_random_tb;
initial begin initial begin
clk[0] <= 1'b0; clk[0] <= 1'b0;
while(1) begin while(1) begin
#0.4159859701 #0.5203860242
clk[0] <= !clk[0]; clk[0] <= !clk[0];
end end
end end
@ -112,7 +112,7 @@ initial begin
$timeformat(-9, 2, "ns", 20); $timeformat(-9, 2, "ns", 20);
$display("Simulation start"); $display("Simulation start");
// //
#332 #416
if(nb_error == 0) begin if(nb_error == 0) begin
$display("Simulation Succeed"); $display("Simulation Succeed");
end else begin end else begin

1309
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v
View File

File diff suppressed because it is too large Load Diff

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit
View File

@ -1 +1 @@
00000000000000000000000011111010000000001000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000

4214
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

5135
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

586
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log
View File

@ -41,9 +41,9 @@ THE SOFTWARE.
Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
VPR FPGA Placement and Routing. VPR FPGA Placement and Routing.
Version: 0.0.0+48b2bff0 Version: 0.0.0+55f7a2c1
Revision: 48b2bff0 Revision: 55f7a2c1
Compiled: 2020-09-27T20:43:27 Compiled: 2020-11-05T12:41:40
Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64
Build Info: release VTR_ASSERT_LEVEL=2 Build Info: release VTR_ASSERT_LEVEL=2
@ -65,35 +65,27 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.00 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB) # Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
# Building complex block graph # Building complex block graph
Warning 6: [LINE 546] false logically-equivalent pin clb[0].I0[1]. Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 546] false logically-equivalent pin clb[0].I0[2]. Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 546] false logically-equivalent pin clb[0].I0[3]. Warning 8: [LINE 588] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 548] false logically-equivalent pin clb[0].I1[1]. Warning 9: [LINE 588] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 548] false logically-equivalent pin clb[0].I1[2]. Warning 10: [LINE 594] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 548] false logically-equivalent pin clb[0].I1[3]. Warning 11: [LINE 594] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 550] false logically-equivalent pin clb[0].I2[1]. Warning 12: [LINE 600] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 550] false logically-equivalent pin clb[0].I2[2]. Warning 13: [LINE 600] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 550] false logically-equivalent pin clb[0].I2[3]. Warning 14: [LINE 606] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 552] false logically-equivalent pin clb[0].I3[1]. Warning 15: [LINE 606] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 552] false logically-equivalent pin clb[0].I3[2]. Warning 16: [LINE 612] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 552] false logically-equivalent pin clb[0].I3[3]. Warning 17: [LINE 612] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 554] false logically-equivalent pin clb[0].I4[1]. Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 554] false logically-equivalent pin clb[0].I4[2]. Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 554] false logically-equivalent pin clb[0].I4[3]. Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 556] false logically-equivalent pin clb[0].I5[1]. Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2].
Warning 22: [LINE 556] false logically-equivalent pin clb[0].I5[2]. # Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
Warning 23: [LINE 556] false logically-equivalent pin clb[0].I5[3].
Warning 24: [LINE 558] false logically-equivalent pin clb[0].I6[1].
Warning 25: [LINE 558] false logically-equivalent pin clb[0].I6[2].
Warning 26: [LINE 558] false logically-equivalent pin clb[0].I6[3].
Warning 27: [LINE 560] false logically-equivalent pin clb[0].I7[1].
Warning 28: [LINE 560] false logically-equivalent pin clb[0].I7[2].
Warning 29: [LINE 560] false logically-equivalent pin clb[0].I7[3].
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.8 MiB)
# Load circuit # Load circuit
# Load circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.3 MiB) # Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Clean circuit # Clean circuit
Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred 0 additional primitive pins as constant generators due to constant inputs Inferred 0 additional primitive pins as constant generators due to constant inputs
@ -102,11 +94,11 @@ Swept output(s) : 0 (0 dangling, 0 constant)
Swept net(s) : 0 Swept net(s) : 0
Swept block(s) : 0 Swept block(s) : 0
Constant Pins Marked: 0 Constant Pins Marked: 0
# Clean circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) # Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
# Compress circuit # Compress circuit
# Compress circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) # Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
# Verify circuit # Verify circuit
# Verify circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) # Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Circuit Statistics: Circuit Statistics:
Blocks: 4 Blocks: 4
.input : 2 .input : 2
@ -121,7 +113,7 @@ Circuit Statistics:
Timing Graph Nodes: 6 Timing Graph Nodes: 6
Timing Graph Edges: 5 Timing Graph Edges: 5
Timing Graph Levels: 4 Timing Graph Levels: 4
# Build Timing Graph took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) # Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Netlist contains 0 clocks Netlist contains 0 clocks
# Load Timing Constraints # Load Timing Constraints
@ -132,7 +124,7 @@ Setting default timing constraints:
Timing constraints created 1 clocks Timing constraints created 1 clocks
Constrained Clock 'virtual_io_clock' (Virtual Clock) Constrained Clock 'virtual_io_clock' (Virtual Clock)
# Load Timing Constraints took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) # Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Timing analysis: ON Timing analysis: ON
Circuit netlist file: top.net Circuit netlist file: top.net
Circuit placement file: top.place Circuit placement file: top.place
@ -201,6 +193,10 @@ RoutingArch.switch_block_type: WILTON
RoutingArch.Fs: 3 RoutingArch.Fs: 3
# Packing # Packing
Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 23: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 24: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 25: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Begin packing 'top.blif'. Begin packing 'top.blif'.
After removing unused inputs... After removing unused inputs...
@ -208,8 +204,12 @@ After removing unused inputs...
Begin prepacking. Begin prepacking.
Finish prepacking. Finish prepacking.
Using inter-cluster delay: 1.33777e-09 Using inter-cluster delay: 1.33777e-09
Packing with pin utilization targets: io:1,1 clb:0.8,1 Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1
Packing with high fanout thresholds: io:128 clb:32 Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32
Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 27: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 28: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 29: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Not enough resources expand FPGA size to (4 x 4) Not enough resources expand FPGA size to (4 x 4)
Complex block 0: 'c' (clb) . Complex block 0: 'c' (clb) .
Complex block 1: 'out:c' (io) . Complex block 1: 'out:c' (io) .
@ -238,23 +238,27 @@ Logic Element (fle) detailed count:
io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667
clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1
Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed.
Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 31: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 32: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 33: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 4 x 4 (2x2) FPGA sized to 4 x 4 (2x2)
Device Utilization: 0.25 (target 1.00) Device Utilization: 0.25 (target 1.00)
Block Utilization: 0.38 Type: io Block Utilization: 0.17 Type: io
Block Utilization: 0.25 Type: clb Block Utilization: 0.25 Type: clb
Netlist conversion complete. Netlist conversion complete.
# Packing took 0.01 seconds (max_rss 10.5 MiB, delta_rss +0.7 MiB) # Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Load Packing # Load Packing
Begin loading packed FPGA netlist file. Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'. Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity) Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.02 seconds). Finished loading packed FPGA netlist file (took 0.01 seconds).
Warning 30: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) # Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
Warning 31: Netlist contains 0 global net to non-global architecture pin connections Warning 35: Netlist contains 0 global net to non-global architecture pin connections
Netlist num_nets: 3 Netlist num_nets: 3
Netlist num_blocks: 4 Netlist num_blocks: 4
@ -266,237 +270,219 @@ Netlist output pins: 1
# Create Device # Create Device
## Build Device Grid ## Build Device Grid
Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 37: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 38: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 39: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 4 x 4: 16 grid tiles (2x2) FPGA sized to 4 x 4: 16 grid tiles (2x2)
Resource usage... Resource usage...
Netlist Netlist
3 blocks of type: io 3 blocks of type: io
Architecture Architecture
8 blocks of type: io 2 blocks of type: io_top
2 blocks of type: io_right
12 blocks of type: io_bottom
2 blocks of type: io_left
Netlist Netlist
1 blocks of type: clb 1 blocks of type: clb
Architecture Architecture
4 blocks of type: clb 4 blocks of type: clb
Device Utilization: 0.25 (target 1.00) Device Utilization: 0.25 (target 1.00)
Physical Tile io: Physical Tile io_top:
Block Utilization: 0.38 Logical Block: io Block Utilization: 1.50 Logical Block: io
Physical Tile io_right:
Block Utilization: 1.50 Logical Block: io
Physical Tile io_bottom:
Block Utilization: 0.25 Logical Block: io
Physical Tile io_left:
Block Utilization: 1.50 Logical Block: io
Physical Tile clb: Physical Tile clb:
Block Utilization: 0.25 Logical Block: clb Block Utilization: 0.25 Logical Block: clb
## Build Device Grid took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.0 MiB) ## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph ## Build tileable routing resource graph
X-direction routing channel width is 40 X-direction routing channel width is 40
Y-direction routing channel width is 40 Y-direction routing channel width is 40
Warning 32: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 33: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 34: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 35: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 36: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. ## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
This is possible on a fringe node based on low Fc_out, N, and certain lengths. RR Graph Nodes: 756
## Build tileable routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) RR Graph Edges: 2930
RR Graph Nodes: 684 # Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
RR Graph Edges: 2780
# Create Device took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB)
# Placement # Placement
## Computing placement delta delay look-up ## Computing placement delta delay look-up
### Build routing resource graph ### Build routing resource graph
Warning 37: in check_rr_node: RR node: 109 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 38: in check_rr_node: RR node: 110 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 39: in check_rr_node: RR node: 293 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 40: in check_rr_node: RR node: 294 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 41: in check_rr_graph: fringe node 2 IPIN at (0,1) has no fanin. ### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB)
This is possible on a fringe node based on low Fc_out, N, and certain lengths. RR Graph Nodes: 756
### Build routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.0 MiB) RR Graph Edges: 2428
RR Graph Nodes: 732
RR Graph Edges: 2188
### Computing delta delays ### Computing delta delays
### Computing delta delays took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) ### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) ## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
There are 3 point to point connections in this circuit. There are 3 point to point connections in this circuit.
BB estimate of min-dist (placement) wire length: 11 BB estimate of min-dist (placement) wire length: 10
Completed placement consistency check successfully. Completed placement consistency check successfully.
Initial placement cost: 1 bb_cost: 0.275 td_cost: 5.6541e-10 Initial placement cost: 1 bb_cost: 0.25 td_cost: 6.04709e-10
Initial placement estimated Critical Path Delay (CPD): 0.69331 ns Initial placement estimated Critical Path Delay (CPD): 0.80931 ns
Initial placement estimated setup Total Negative Slack (sTNS): -0.69331 ns Initial placement estimated setup Total Negative Slack (sTNS): -0.80931 ns
Initial placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns Initial placement estimated setup Worst Negative Slack (sWNS): -0.80931 ns
Initial placement estimated setup slack histogram: Initial placement estimated setup slack histogram:
[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** [ -8.1e-10: -8.1e-10) 1 (100.0%) |**************************************************
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
Placement contains 0 placement macros involving 0 blocks (average macro size -nan) Placement contains 0 placement macros involving 0 blocks (average macro size -nan)
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
5.6e-01 0.892 0.21 5.1708e-10 0.693 -0.693 -0.693 1.000 0.0754 3.0 1.00 6 0.500 9.2e-01 0.857 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0425 3.0 1.00 6 0.950
2.8e-01 1.001 0.25 5.8474e-10 0.693 -0.693 -0.693 1.000 0.1044 3.0 1.00 12 0.500 8.8e-01 1.031 0.22 5.2788e-10 0.693 -0.693 -0.693 1.000 0.1248 3.0 1.00 12 0.500
1.4e-01 0.828 0.19 5.1901e-10 0.751 -0.751 -0.751 0.833 0.0971 3.0 1.00 18 0.900 4.4e-01 0.977 0.20 4.5978e-10 0.693 -0.693 -0.693 1.000 0.0478 3.0 1.00 18 0.500
1.3e-01 1.119 0.21 5.3388e-10 0.693 -0.693 -0.693 0.500 0.0412 3.0 1.00 24 0.950 2.2e-01 1.296 0.24 6.1181e-10 0.577 -0.577 -0.577 0.833 0.1114 3.0 1.00 24 0.900
1.2e-01 1.017 0.24 5.3998e-10 0.693 -0.693 -0.693 0.833 0.0366 3.0 1.00 30 0.900 2.0e-01 0.807 0.21 5.1793e-10 0.809 -0.809 -0.809 0.833 0.1585 3.0 1.00 30 0.900
1.1e-01 0.960 0.24 5.3641e-10 0.693 -0.693 -0.693 1.000 0.0433 3.0 1.00 36 0.500 1.8e-01 1.284 0.23 4.5908e-10 0.577 -0.577 -0.577 1.000 0.1344 3.0 1.00 36 0.500
5.4e-02 0.970 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0405 3.0 1.00 42 0.950 8.9e-02 0.981 0.23 4.8318e-10 0.635 -0.635 -0.635 1.000 0.0703 3.0 1.00 42 0.500
5.1e-02 0.974 0.19 4.4803e-10 0.635 -0.635 -0.635 0.667 0.0470 3.0 1.00 48 0.950 4.4e-02 0.906 0.23 4.617e-10 0.693 -0.693 -0.693 0.833 0.0159 3.0 1.00 48 0.900
4.9e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 54 0.950 4.0e-02 0.915 0.20 4.3008e-10 0.693 -0.693 -0.693 1.000 0.0692 3.0 1.00 54 0.500
4.6e-02 1.063 0.19 4.5701e-10 0.635 -0.635 -0.635 0.500 0.0549 2.7 2.12 60 0.950 2.0e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 3.0 1.00 60 0.950
4.4e-02 1.019 0.21 4.9794e-10 0.693 -0.693 -0.693 0.667 0.0458 2.8 1.56 66 0.950 1.9e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.7 2.12 66 0.950
4.2e-02 1.043 0.21 5.1943e-10 0.693 -0.693 -0.693 0.667 0.0215 3.0 1.00 72 0.950 1.8e-02 0.982 0.17 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0357 1.9 4.68 72 0.950
4.0e-02 0.903 0.18 4.7533e-10 0.751 -0.751 -0.751 0.500 0.0052 3.0 1.00 78 0.950 1.7e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.4 3.14 78 0.950
3.8e-02 1.042 0.20 4.4941e-10 0.693 -0.693 -0.693 0.333 0.0000 3.0 1.00 84 0.950 1.6e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.7 5.42 84 0.950
3.6e-02 1.000 0.20 4.2544e-10 0.635 -0.635 -0.635 0.167 0.0000 2.7 2.12 90 0.950 1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 7.08 90 0.950
3.4e-02 1.069 0.22 4.4576e-10 0.635 -0.635 -0.635 0.667 0.0458 1.9 4.68 96 0.950 1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 6.82 96 0.950
3.2e-02 0.969 0.21 4.6916e-10 0.693 -0.693 -0.693 0.667 0.0361 2.4 3.14 102 0.950 1.4e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.4 6.54 102 0.950
3.1e-02 0.968 0.19 4.7066e-10 0.693 -0.693 -0.693 0.500 0.0537 2.9 1.24 108 0.950 1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.3 7.07 108 0.950
2.9e-02 0.997 0.18 4.322e-10 0.635 -0.635 -0.635 0.500 0.0000 3.0 1.00 114 0.950 1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.54 114 0.950
2.8e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 120 0.950 1.2e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.2 7.30 120 0.950
2.6e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 2.7 2.12 126 0.950 1.1e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 126 0.800
2.5e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 2.8 1.56 132 0.950 9.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 132 0.950
2.4e-02 0.994 0.18 4.0763e-10 0.635 -0.635 -0.635 0.167 0.0000 2.5 2.62 138 0.950 8.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 138 0.950
2.3e-02 0.996 0.18 3.9202e-10 0.635 -0.635 -0.635 0.500 0.0064 1.8 5.05 144 0.950 8.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 144 0.950
2.1e-02 1.000 0.18 4.0247e-10 0.635 -0.635 -0.635 0.333 0.0000 2.0 4.66 150 0.950 7.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.99 150 0.950
2.0e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.7 5.39 156 0.950 7.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 156 0.950
1.9e-02 1.071 0.20 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 7.06 162 0.950 7.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0000 1.1 7.79 162 0.950
1.8e-02 0.967 0.18 5.0741e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.79 168 0.950 6.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.833 0.0000 1.3 6.95 168 0.900
1.7e-02 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 174 0.950 6.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.8 5.16 174 0.950
1.7e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 180 0.950 5.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.95 180 0.950
1.6e-02 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 186 0.950 5.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 8.00 186 0.950
1.5e-02 0.989 0.18 3.5797e-10 0.635 -0.635 -0.635 0.667 0.0076 1.1 7.79 192 0.950 5.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 192 0.950
1.4e-02 1.000 0.18 3.8602e-10 0.635 -0.635 -0.635 0.667 0.0000 1.3 6.95 198 0.950 4.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.1 7.79 198 0.950
1.3e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.6 5.92 204 0.950 4.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 204 0.950
1.3e-02 0.991 0.18 3.7094e-10 0.635 -0.635 -0.635 0.500 0.0078 1.4 6.51 210 0.950 4.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 210 0.950
1.2e-02 0.995 0.18 3.809e-10 0.635 -0.635 -0.635 0.333 0.0113 1.5 6.21 216 0.950 4.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 216 0.950
1.2e-02 1.000 0.18 4.1466e-10 0.693 -0.693 -0.693 0.167 0.0000 1.3 6.78 222 0.950 4.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 222 0.950
1.1e-02 0.971 0.18 3.491e-10 0.693 -0.693 -0.693 0.500 0.0000 1.0 8.00 228 0.950 3.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 7.99 228 0.950
1.0e-02 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 234 0.950 3.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 234 0.950
9.9e-03 1.015 0.18 4.086e-10 0.635 -0.635 -0.635 0.333 0.0205 1.0 8.00 240 0.950 3.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 240 0.950
9.4e-03 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 246 0.950 3.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 246 0.950
9.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.667 0.0000 1.0 8.00 252 0.950 3.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.79 252 0.950
8.5e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.333 0.0000 1.2 7.21 258 0.950 2.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 258 0.800
8.1e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.66 264 0.950 2.3e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 264 0.950
7.7e-03 1.000 0.18 3.8297e-10 0.635 -0.635 -0.635 0.167 0.0000 1.2 7.43 270 0.950 2.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 270 0.950
7.3e-03 0.992 0.18 3.6408e-10 0.635 -0.635 -0.635 0.667 0.0090 1.0 8.00 276 0.950 2.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 276 0.800
6.9e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.500 0.0000 1.2 7.21 282 0.950 1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 282 0.950
6.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 6.95 288 0.950 1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 288 0.000
6.3e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.4 6.68 294 0.950
5.9e-03 1.000 0.18 3.8973e-10 0.635 -0.635 -0.635 0.500 0.0000 1.5 6.39 300 0.950
5.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.5 6.08 306 0.950
5.4e-03 0.995 0.18 3.788e-10 0.635 -0.635 -0.635 0.500 0.0079 1.4 6.66 312 0.950
5.1e-03 1.000 0.18 3.8986e-10 0.635 -0.635 -0.635 0.167 0.0000 1.5 6.37 318 0.950
4.8e-03 1.000 0.18 3.8095e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.77 324 0.950
4.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.55 330 0.950
4.4e-03 0.995 0.18 3.7402e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.31 336 0.950
4.1e-03 0.986 0.18 3.5684e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 7.06 342 0.950
3.9e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 348 0.950
3.7e-03 0.985 0.18 3.5034e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 354 0.950
3.6e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 360 0.950
3.4e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 366 0.950
3.2e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.79 372 0.950
3.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.57 378 0.950
2.9e-03 0.995 0.18 3.7386e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.33 384 0.950
2.8e-03 0.990 0.18 3.6614e-10 0.635 -0.635 -0.635 0.500 0.0082 1.3 7.08 390 0.950
2.6e-03 1.000 0.18 3.8688e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.82 396 0.950
2.5e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 402 0.950
2.4e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.000 0.0000 1.1 7.79 408 0.950
2.2e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 414 0.950
2.1e-03 0.995 0.18 3.7067e-10 0.635 -0.635 -0.635 0.500 0.0088 1.1 7.79 420 0.950
2.0e-03 0.985 0.18 3.5227e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.57 426 0.950
1.9e-03 0.992 0.18 3.6418e-10 0.635 -0.635 -0.635 0.333 0.0110 1.0 7.99 432 0.950
1.8e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 438 0.950
1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 444 0.950
1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 450 0.000
BB estimate of min-dist (placement) wire length: 7 BB estimate of min-dist (placement) wire length: 6
Completed placement consistency check successfully. Completed placement consistency check successfully.
Swaps called: 454 Swaps called: 292
Placement estimated critical path delay: 0.63531 ns Placement estimated critical path delay: 0.57731 ns
Placement estimated setup Total Negative Slack (sTNS): -0.63531 ns Placement estimated setup Total Negative Slack (sTNS): -0.57731 ns
Placement estimated setup Worst Negative Slack (sWNS): -0.63531 ns Placement estimated setup Worst Negative Slack (sWNS): -0.57731 ns
Placement estimated setup slack histogram: Placement estimated setup slack histogram:
[ -6.4e-10: -6.4e-10) 1 (100.0%) |************************************************** [ -5.8e-10: -5.8e-10) 1 (100.0%) |**************************************************
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | [ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
Placement cost: 1, bb_cost: 0.175, td_cost: 4.4941e-10, Placement cost: 1, bb_cost: 0.15, td_cost: 3.9141e-10,
Placement resource usage: Placement resource usage:
io implemented as io : 3 io implemented as io_bottom: 2
clb implemented as clb: 1 io implemented as io_left : 1
clb implemented as clb : 1
Placement number of temperatures: 75 Placement number of temperatures: 48
Placement total # of swap attempts: 454 Placement total # of swap attempts: 292
Swaps accepted: 208 (45.8 %) Swaps accepted: 125 (42.8 %)
Swaps rejected: 246 (54.2 %) Swaps rejected: 167 (57.2 %)
Swaps aborted : 0 ( 0.0 %) Swaps aborted : 0 ( 0.0 %)
Aborted Move Reasons: Aborted Move Reasons:
# Placement took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.5 MiB) # Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB)
# Routing # Routing
## Build tileable routing resource graph ## Build tileable routing resource graph
X-direction routing channel width is 40 X-direction routing channel width is 40
Y-direction routing channel width is 40 Y-direction routing channel width is 40
Warning 42: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 43: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 44: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 45: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 46: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. ## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB)
This is possible on a fringe node based on low Fc_out, N, and certain lengths. RR Graph Nodes: 756
## Build tileable routing resource graph took 0.00 seconds (max_rss 11.6 MiB, delta_rss +0.0 MiB) RR Graph Edges: 2930
RR Graph Nodes: 684
RR Graph Edges: 2780
Confirming router algorithm: TIMING_DRIVEN. Confirming router algorithm: TIMING_DRIVEN.
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ
(sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
1 0.0 0.0 0 80 3 3 0 ( 0.000%) 6 ( 1.2%) 0.693 -0.6933 -0.693 0.000 0.000 N/A 1 0.0 0.0 0 203 3 3 1 ( 0.132%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A
2 0.0 0.5 0 86 1 1 0 ( 0.000%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A
Restoring best routing Restoring best routing
Critical path: 0.69331 ns Critical path: 0.86731 ns
Successfully routed after 1 routing iterations. Successfully routed after 2 routing iterations.
Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 80 total_heap_pops: 45 Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187
# Routing took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.1 MiB) # Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB)
Checking to ensure routing is legal... Checking to ensure routing is legal...
Completed routing consistency check successfully. Completed routing consistency check successfully.
Serial number (magic cookie) for the routing is: -11536 Serial number (magic cookie) for the routing is: -18854
Circuit successfully routed with a channel width factor of 40. Circuit successfully routed with a channel width factor of 40.
Average number of bends per net: 0.333333 Maximum # of bends: 1 Average number of bends per net: 2.00000 Maximum # of bends: 3
Number of global nets: 0 Number of global nets: 0
Number of routed nets (nonglobal): 3 Number of routed nets (nonglobal): 3
Wire length results (in units of 1 clb segments)... Wire length results (in units of 1 clb segments)...
Total wirelength: 6, average net length: 2.00000 Total wirelength: 12, average net length: 4.00000
Maximum net length: 3 Maximum net length: 6
Wire length results in terms of physical segments... Wire length results in terms of physical segments...
Total wiring segments used: 5, average wire segments per net: 1.66667 Total wiring segments used: 9, average wire segments per net: 3.00000
Maximum segments used by a net: 2 Maximum segments used by a net: 4
Total local nets with reserved CLB opins: 0 Total local nets with reserved CLB opins: 0
Routing channel utilization histogram: Routing channel utilization histogram:
@ -510,17 +496,17 @@ Routing channel utilization histogram:
[ 0.2: 0.3) 0 ( 0.0%) | [ 0.2: 0.3) 0 ( 0.0%) |
[ 0.1: 0.2) 0 ( 0.0%) | [ 0.1: 0.2) 0 ( 0.0%) |
[ 0: 0.1) 18 (100.0%) |************************************************ [ 0: 0.1) 18 (100.0%) |************************************************
Maximum routing channel utilization: 0.075 at (1,0) Maximum routing channel utilization: 0.05 at (1,0)
X - Directed channels: j max occ ave occ capacity X - Directed channels: j max occ ave occ capacity
---- ------- ------- -------- ---- ------- ------- --------
0 3 1.250 40 0 2 0.750 40
1 0 0.000 40 1 2 0.500 40
2 0 0.000 40 2 0 0.000 40
Y - Directed channels: i max occ ave occ capacity Y - Directed channels: i max occ ave occ capacity
---- ------- ------- -------- ---- ------- ------- --------
0 1 0.250 40 0 2 0.750 40
1 0 0.000 40 1 3 1.000 40
2 0 0.000 40 2 0 0.000 40
Total tracks in x-direction: 120, in y-direction: 120 Total tracks in x-direction: 120, in y-direction: 120
@ -530,55 +516,55 @@ Logic area (in minimum width transistor areas, excludes I/Os and empty grid tile
Total used logic block area: 53894 Total used logic block area: 53894
Routing area (in minimum width transistor areas)... Routing area (in minimum width transistor areas)...
Total routing area: 22261.4, per logic tile: 1391.34 Total routing area: 23072.6, per logic tile: 1442.04
Segment usage by type (index): type utilization Segment usage by type (index): type utilization
---- ----------- ---- -----------
0 0.0833 0 0.0833
1 0.0278 1 0
2 0 2 0.0208
Segment usage by length: length utilization Segment usage by length: length utilization
------ ----------- ------ -----------
1 0.0833 1 0.0833
2 0.0278 2 0
4 0 4 0.0208
Hold Worst Negative Slack (hWNS): 0 ns Hold Worst Negative Slack (hWNS): 0 ns
Hold Total Negative Slack (hTNS): 0 ns Hold Total Negative Slack (hTNS): 0 ns
Hold slack histogram: Hold slack histogram:
[ 5.5e-10: 5.5e-10) 1 (100.0%) |************************************************** [ 7.3e-10: 7.3e-10) 1 (100.0%) |**************************************************
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | [ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
Final critical path: 0.69331 ns, Fmax: 1442.36 MHz Final critical path: 0.86731 ns, Fmax: 1152.99 MHz
Setup Worst Negative Slack (sWNS): -0.69331 ns Setup Worst Negative Slack (sWNS): -0.86731 ns
Setup Total Negative Slack (sTNS): -0.69331 ns Setup Total Negative Slack (sTNS): -0.86731 ns
Setup slack histogram: Setup slack histogram:
[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** [ -8.7e-10: -8.7e-10) 1 (100.0%) |**************************************************
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
Timing analysis took 0.000488774 seconds (0.000430824 STA, 5.795e-05 slack) (80 full updates: 78 setup, 0 hold, 2 combined). Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
VPR suceeded VPR suceeded
The entire flow of VPR took 0.08 seconds (max_rss 11.9 MiB) The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
@ -586,17 +572,16 @@ Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml --file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'...
Read OpenFPGA architecture Read OpenFPGA architecture
Warning 47: Automatically set circuit model 'frac_lut4' to be default in its type. Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type.
Warning 48: Automatically set circuit model 'sky130_fd_sc_hd__sdfxbp_1' to be default in its type. Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type.
Warning 49: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type.
Warning 50: Automatically set circuit model 'GPIO' to be default in its type.
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.3 MiB) Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB)
Check circuit library Check circuit library
Checking circuit library passed. Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models! Found 0 errors when checking configurable memory circuit models!
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
@ -605,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml --file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
@ -634,9 +619,9 @@ Check pb_graph annotation for physical nodes and pins passed.
Binded 4 routing resource graph switches to circuit models Binded 4 routing resource graph switches to circuit models
Binded 3 routing segments to circuit models Binded 3 routing segments to circuit models
Binded 2 direct connections to circuit models Binded 2 direct connections to circuit models
Annotating rr_node with routed nets...Done with 11 nodes mapping Annotating rr_node with routed nets...Done with 15 nodes mapping
Annotating previous nodes for rr_node...Warning 51: Override the previous node '89' by previous node '90' for node '37' with in routing context annotation! Annotating previous nodes for rr_node...Warning 55: Override the previous node '139' by previous node '137' for node '84' with in routing context annotation!
Done with 14 nodes mapping Done with 18 nodes mapping
# Build General Switch Block(GSB) annotation on top of routing resource graph # Build General Switch Block(GSB) annotation on top of routing resource graph
[11%] Backannotated GSB[0][0] [11%] Backannotated GSB[0][0]
[22%] Backannotated GSB[0][1] [22%] Backannotated GSB[0][1]
@ -648,7 +633,7 @@ Done with 14 nodes mapping
[88%] Backannotated GSB[2][1] [88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2] [100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs). Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) # Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB) # Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted edges for GSB[0][0] [11%] Sorted edges for GSB[0][0]
[22%] Sorted edges for GSB[0][1] [22%] Sorted edges for GSB[0][1]
@ -660,9 +645,9 @@ Backannotated 9 General Switch Blocks (GSBs).
[88%] Sorted edges for GSB[2][1] [88%] Sorted edges for GSB[2][1]
[100%] Sorted edges for GSB[2][2] [100%] Sorted edges for GSB[2][2]
Sorted edges for 9 General Switch Blocks (GSBs). Sorted edges for 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers # Build a library of physical multiplexers
Built a multiplexer library of 14 physical multiplexers. Built a multiplexer library of 15 physical multiplexers.
Maximum multiplexer size is 17. Maximum multiplexer size is 17.
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) # Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
# Build the annotation about direct connection between tiles # Build the annotation about direct connection between tiles
@ -670,8 +655,8 @@ Built 6 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) # Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
Building annotation for mapped blocks on grid locations...Done Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results User specified the operating clock frequency to use VPR results
Use VPR critical path delay 8.31972e-19 [ns] with a 20 [%] slack in OpenFPGA. Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA.
Will apply operating clock frequency 1201.96 [MHz] to simulations Will apply operating clock frequency 960.825 [MHz] to simulations
User specified the number of operating clock cycles to be inferred from signal activities User specified the number of operating clock cycles to be inferred from signal activities
Average net density: 0.42 Average net density: 0.42
Median net density: 0.00 Median net density: 0.00
@ -694,63 +679,65 @@ Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
Read Fabric Key Read Fabric Key
Read Fabric Key took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Build fabric module graph Build fabric module graph
# Build constant generator modules # Build constant generator modules
# Build constant generator modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) # Build constant generator modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build user-defined modules # Build user-defined modules
# Build user-defined modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) # Build user-defined modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build essential (inverter/buffer/logic gate) modules # Build essential (inverter/buffer/logic gate) modules
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) # Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build local encoder (for multiplexers) modules # Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) # Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules # Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.3 MiB) # Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
# Build Look-Up Table (LUT) modules # Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) # Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB)
# Build wire modules # Build wire modules
# Build wire modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) # Build wire modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB)
# Build memory modules # Build memory modules
# Build memory modules took 0.00 seconds (max_rss 13.1 MiB, delta_rss +0.3 MiB) # Build memory modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB)
# Build grid modules # Build grid modules
Building logical tiles...Done Building logical tiles...Done
Building physical tiles...Done Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 13.6 MiB, delta_rss +0.5 MiB) # Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB)
# Build unique routing modules... # Build unique routing modules...
# Build unique routing modules... took 0.01 seconds (max_rss 15.9 MiB, delta_rss +2.3 MiB) # Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
# Build FPGA fabric module # Build FPGA fabric module
## Add grid instances to top module ## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) ## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module ## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) ## Add switch block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module ## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module ## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add module nets between grids and GSBs ## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.5 MiB) ## Add module nets between grids and GSBs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.5 MiB)
## Add module nets for inter-tile connections ## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.0 MiB) ## Add module nets for inter-tile connections took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses ## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.1 MiB) ## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +0.9 MiB) # Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB)
Build fabric module graph took 0.02 seconds (max_rss 16.8 MiB, delta_rss +4.2 MiB) Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: repack Command line to execute: repack
Confirm selected options when call command 'repack': Confirm selected options when call command 'repack':
--verbose: off --verbose: off
Build routing resource graph for the physical implementation of logical tile Build routing resource graph for the physical implementation of logical tile
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.3 MiB) Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB)
Repack clustered blocks to physical implementation of logical tile Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'c'...Done Repack clustered block 'c'...Done
Repack clustered block 'out:c'...Done Repack clustered block 'out:c'...Done
Repack clustered block 'a'...Done Repack clustered block 'a'...Done
Repack clustered block 'b'...Done Repack clustered block 'b'...Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs Build truth tables for physical LUTs
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB)
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
@ -766,10 +753,10 @@ Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done
Build fabric-independent bitstream for implementation 'top' Build fabric-independent bitstream for implementation 'top'
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Warning 52: Directory path is empty and nothing will be created. Warning 56: Directory path is empty and nothing will be created.
Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Command line to execute: build_fabric_bitstream Command line to execute: build_fabric_bitstream
@ -780,7 +767,7 @@ Build fabric dependent bitstream
Build fabric dependent bitstream Build fabric dependent bitstream
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.3 MiB)
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
@ -788,9 +775,9 @@ Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit --file, -f: fabric_bitstream.bit
--format: plain_text --format: plain_text
--verbose: off --verbose: off
Warning 53: Directory path is empty and nothing will be created. Warning 57: Directory path is empty and nothing will be created.
Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
@ -798,9 +785,9 @@ Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml --file, -f: fabric_bitstream.xml
--format: xml --format: xml
--verbose: off --verbose: off
Warning 54: Directory path is empty and nothing will be created. Warning 58: Directory path is empty and nothing will be created.
Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
@ -852,22 +839,23 @@ Done
Writing logical tiles...Done Writing logical tiles...Done
Building physical tiles... Building physical tiles...
Writing Verilog Netlist './SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done
Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
Building physical tiles...Done Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 70 Verilog modules in total Written 73 Verilog modules in total
Write Verilog netlists for FPGA fabric Write Verilog netlists for FPGA fabric
took 0.15 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
Confirm selected options when call command 'write_verilog_testbench': Confirm selected options when call command 'write_verilog_testbench':
--file, -f: ./SRC --file, -f: ./SRC
--fabric_netlist_file_path: off
--reference_benchmark_file_path: top_output_verilog.v --reference_benchmark_file_path: top_output_verilog.v
--print_top_testbench: on --print_top_testbench: on
--fast_configuration: off --fast_configuration: off
@ -876,22 +864,22 @@ Confirm selected options when call command 'write_verilog_testbench':
--print_simulation_ini: ./SimulationDeck/simulation_deck.ini --print_simulation_ini: ./SimulationDeck/simulation_deck.ini
--explicit_port_mapping: on --explicit_port_mapping: on
--verbose: off --verbose: off
Warning 55: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled Warning 59: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
Write Verilog testbenches for FPGA fabric Write Verilog testbenches for FPGA fabric
Warning 56: Directory './SRC' already exists. Will overwrite contents Warning 60: Directory './SRC' already exists. Will overwrite contents
# Write pre-configured FPGA top-level Verilog netlist for design 'top' # Write pre-configured FPGA top-level Verilog netlist for design 'top'
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) # Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' # Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
Will use 2010 configuration clock cycles to top testbench Will use 2107 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
Succeed to create directory './SimulationDeck' Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric Write Verilog testbenches for FPGA fabric
took 0.03 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
Command line to execute: exit Command line to execute: exit
@ -899,6 +887,6 @@ Confirm selected options when call command 'exit':
Finish execution with 0 errors Finish execution with 0 errors
The entire OpenFPGA flow took 0.22 seconds The entire OpenFPGA flow took 0.25 seconds
Thank you for using OpenFPGA! Thank you for using OpenFPGA!

68
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml
View File

@ -1,36 +1,38 @@
<?xml version="1.0" ?> <?xml version="1.0" ?>
<fabric_key> <fabric_key>
<key id="0" alias="sb_2__2_"/> <region id="0">
<key id="1" alias="cbx_2__2_"/> <key id="0" alias="sb_2__2_"/>
<key id="2" alias="grid_io_top_2__3_"/> <key id="1" alias="cbx_2__2_"/>
<key id="3" alias="sb_1__2_"/> <key id="2" alias="grid_io_top_top_2__3_"/>
<key id="4" alias="cbx_1__2_"/> <key id="3" alias="sb_1__2_"/>
<key id="5" alias="grid_io_top_1__3_"/> <key id="4" alias="cbx_1__2_"/>
<key id="6" alias="sb_0__2_"/> <key id="5" alias="grid_io_top_top_1__3_"/>
<key id="7" alias="cby_0__2_"/> <key id="6" alias="sb_0__2_"/>
<key id="8" alias="grid_io_left_0__2_"/> <key id="7" alias="cby_0__2_"/>
<key id="9" alias="grid_clb_1__2_"/> <key id="8" alias="grid_io_left_left_0__2_"/>
<key id="10" alias="cby_1__2_"/> <key id="9" alias="grid_clb_1__2_"/>
<key id="11" alias="grid_clb_2__2_"/> <key id="10" alias="cby_1__2_"/>
<key id="12" alias="cby_2__2_"/> <key id="11" alias="grid_clb_2__2_"/>
<key id="13" alias="grid_io_right_3__2_"/> <key id="12" alias="cby_2__2_"/>
<key id="14" alias="sb_2__1_"/> <key id="13" alias="grid_io_right_right_3__2_"/>
<key id="15" alias="cbx_2__1_"/> <key id="14" alias="sb_2__1_"/>
<key id="16" alias="sb_1__1_"/> <key id="15" alias="cbx_2__1_"/>
<key id="17" alias="cbx_1__1_"/> <key id="16" alias="sb_1__1_"/>
<key id="18" alias="sb_0__1_"/> <key id="17" alias="cbx_1__1_"/>
<key id="19" alias="cby_0__1_"/> <key id="18" alias="sb_0__1_"/>
<key id="20" alias="grid_io_left_0__1_"/> <key id="19" alias="cby_0__1_"/>
<key id="21" alias="grid_clb_1__1_"/> <key id="20" alias="grid_io_left_left_0__1_"/>
<key id="22" alias="cby_1__1_"/> <key id="21" alias="grid_clb_1__1_"/>
<key id="23" alias="grid_clb_2__1_"/> <key id="22" alias="cby_1__1_"/>
<key id="24" alias="cby_2__1_"/> <key id="23" alias="grid_clb_2__1_"/>
<key id="25" alias="grid_io_right_3__1_"/> <key id="24" alias="cby_2__1_"/>
<key id="26" alias="sb_2__0_"/> <key id="25" alias="grid_io_right_right_3__1_"/>
<key id="27" alias="cbx_2__0_"/> <key id="26" alias="sb_2__0_"/>
<key id="28" alias="grid_io_bottom_2__0_"/> <key id="27" alias="cbx_2__0_"/>
<key id="29" alias="sb_1__0_"/> <key id="28" alias="grid_io_bottom_bottom_2__0_"/>
<key id="30" alias="cbx_1__0_"/> <key id="29" alias="sb_1__0_"/>
<key id="31" alias="grid_io_bottom_1__0_"/> <key id="30" alias="cbx_1__0_"/>
<key id="32" alias="sb_0__0_"/> <key id="31" alias="grid_io_bottom_bottom_1__0_"/>
<key id="32" alias="sb_0__0_"/>
</region>
</fabric_key> </fabric_key>

28
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml
View File

@ -148,7 +148,7 @@
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v"> <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@ -174,27 +174,25 @@
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v"> <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<!-- <port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> -->
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Q_N" size="1"/> <port type="output" prefix="Q_N" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/std_cell_extract.v"> <circuit_model type="iopad" name="EMBEDDED_IO" prefix="EMBEDDED_IO" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" /> <port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true" /> <port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="en" lib_name="mem_out" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/> <port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true" /> <port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true" /> <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="input" prefix="outpad" lib_name="in" size="1"/> <port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
<port type="output" prefix="inpad" lib_name="out" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -220,20 +218,16 @@
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> <pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxbp_1"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

250
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml
View File

@ -33,7 +33,7 @@
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
@ -60,7 +60,8 @@
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="1" area="0"> <!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
@ -68,72 +69,117 @@
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="bottom">io_top.outpad io_top.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
<!-- Bottom-side has 6 I/O per tile -->
<tile name="io_bottom" capacity="6" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894"> <tile name="clb" area="53894">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I0" num_pins="4" equivalent="full"/> <input name="I0" num_pins="3" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/> <input name="I0i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="4" equivalent="full"/> <input name="I1" num_pins="3" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/> <input name="I1i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="4" equivalent="full"/> <input name="I2" num_pins="3" equivalent="full"/>
<input name="I5" num_pins="4" equivalent="full"/> <input name="I2i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="4" equivalent="full"/> <input name="I3" num_pins="3" equivalent="full"/>
<input name="I7" num_pins="4" equivalent="full"/> <input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>
<input name="scin" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="regout" num_pins="1"/> <output name="regout" num_pins="1"/>
<output name="scout" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="regin" fc_type="frac" fc_val="0"/> <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
<fc_override port_name="regout" fc_type="frac" fc_val="0"/> <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
<fc_override port_name="scin" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="scout" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<!--pinlocations pattern="spread"/--> <!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">clb.clk</loc> <loc side="left">clb.clk</loc>
<loc side="top">clb.regin clb.scin</loc> <loc side="top">clb.regin clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
<loc side="right">clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3</loc> <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7</loc> <loc side="bottom">clb.regout clb.sc_out</loc>
</pinlocations> </pinlocations>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="2.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="12x12" width="14" height="14">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <row type="io_top" starty="H-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <row type="io_bottom" starty="0" priority="100"/>
<!--Fill with 'clb'--> <col type="io_left" startx="0" priority="100"/>
<fill type="clb" priority="10"/> <col type="io_right" startx="W-1" priority="100"/>
</fixed_layout>
<fixed_layout name="20x10" width="22" height="12">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
@ -210,12 +256,10 @@
</segmentlist> </segmentlist>
<directlist> <directlist>
<direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/> <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
<direct name="scan_chain" from_pin="clb.scout" to_pin="clb.scin" x_offset="0" y_offset="-1" z_offset="0"/> <direct name="scan_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist> </directlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define input pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -266,39 +310,37 @@
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!-- -Due to the absence of local routing,
area is 60 L^2 yields a tile area of 84375 MWTAs. the 4 inputs of fracturable LUT4 are no longer equivalent,
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area because the 4th input can not be switched when the dual-LUT3 modes are used.
This means that only 37% of our area is in the general routing, and 63% is inside the logic So pin equivalence should be applied to the first 3 inputs only
block. Note that the crossbar / local interconnect is considered part of the logic block -->
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb"> <pb_type name="clb">
<input name="I0" num_pins="4" equivalent="full"/> <input name="I0" num_pins="3" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/> <input name="I0i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="4" equivalent="full"/> <input name="I1" num_pins="3" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/> <input name="I1i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="4" equivalent="full"/> <input name="I2" num_pins="3" equivalent="full"/>
<input name="I5" num_pins="4" equivalent="full"/> <input name="I2i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="4" equivalent="full"/> <input name="I3" num_pins="3" equivalent="full"/>
<input name="I7" num_pins="4" equivalent="full"/> <input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>
<input name="scin" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="regout" num_pins="1"/> <output name="regout" num_pins="1"/>
<output name="scout" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
@ -307,20 +349,20 @@
<pb_type name="fle" num_pb="8"> <pb_type name="fle" num_pb="8">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>
<input name="scin" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<output name="regout" num_pins="1"/> <output name="regout" num_pins="1"/>
<output name="scout" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disabled_in_pack="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>
<input name="scin" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<output name="regout" num_pins="1"/> <output name="regout" num_pins="1"/>
<output name="scout" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
@ -350,9 +392,9 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.scin" output="ff[0].DI"/> <direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/> <direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct4" input="ff[1].Q" output="fabric.scout"/> <direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff[1].Q" output="fabric.regout"/> <direct name="direct5" input="ff[1].Q" output="fabric.regout"/>
<direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/> <direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
@ -375,10 +417,10 @@
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct3" input="fle.regin" output="fabric.regin"/> <direct name="direct3" input="fle.regin" output="fabric.regin"/>
<direct name="direct4" input="fle.scin" output="fabric.scin"/> <direct name="direct4" input="fle.sc_in" output="fabric.sc_in"/>
<direct name="direct5" input="fabric.out" output="fle.out"/> <direct name="direct5" input="fabric.out" output="fle.out"/>
<direct name="direct7" input="fabric.regout" output="fle.regout"/> <direct name="direct7" input="fabric.regout" output="fle.regout"/>
<direct name="direct8" input="fabric.scout" output="fle.scout"/> <direct name="direct8" input="fabric.sc_out" output="fle.sc_out"/>
<direct name="direct9" input="fle.clk" output="fabric.clk"/> <direct name="direct9" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
@ -534,30 +576,56 @@
<!-- Define shift register end --> <!-- Define shift register end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use direct connections to reduce the area to the most
The delays below come from Stratix IV. the delay through a connection block The global local routing is going to compensate the loss in routability
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps -->
delay on the connection block input mux (modeled by Ian Kuon), so the remaining <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
delay within the crossbar is 95 ps. <!-- TODO: Timing should be backannotated from post-PnR results -->
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<direct name="direct_fle0" input="clb.I0" output="fle[0:0].in">
</direct> </direct>
<direct name="direct_fle1" input="clb.I1" output="fle[1:1].in"> <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2" output="fle[2:2].in"> <direct name="direct_fle1" input="clb.I1" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3" output="fle[3:3].in"> <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4" output="fle[4:4].in"> <direct name="direct_fle2" input="clb.I2" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5" output="fle[5:5].in"> <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6" output="fle[6:6].in"> <direct name="direct_fle3" input="clb.I3" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7" output="fle[7:7].in"> <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -581,13 +649,13 @@
<!--pack_pattern name="chain" in_port="fle[6:0].regout" out_port="fle[7:1].regin"/--> <!--pack_pattern name="chain" in_port="fle[6:0].regout" out_port="fle[7:1].regin"/-->
</direct> </direct>
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/> <delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].scout" output="clb.scout"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>
<direct name="scan_chain_link" input="fle[6:0].scout" output="fle[7:1].scin"> <direct name="scan_chain_link" input="fle[6:0].sc_out" output="fle[7:1].sc_in">
</direct> </direct>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->

63
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v Normal file
View File

@ -0,0 +1,63 @@
`timescale 1ns/1ps
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule
//
//
//
//
module EMBEDDED_IO (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR //
);
assign FPGA_IN = SOC_IN;
assign SOC_OUT = FPGA_OUT;
assign SOC_DIR = FPGA_DIR;
endmodule
//
//
//
module GPIN (
inout A, //
output Y //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule
//
//
//
module GPOUT (
inout Y, //
input A //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule

11
FPGA22_HIER_SKY_PNR/README.md
View File

@ -2,7 +2,14 @@ FPGA22_HIER_SKY_PNR
==================== ====================
2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`. 2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
Utilization set to 60%
Updates
-------------------
- **Merged `grid_io` modules with connection blocks**
- **Pre-routed scan chain signals**
- **Created `carry_chain` feedthrough between `grid_clb` modules**
- Prerouting global signals (`Test_en`)
- Prerouting clock signals
Directory Structure Directory Structure
------------------- -------------------
@ -21,4 +28,4 @@ Pending
--------- ---------
- DRC SignOff - DRC SignOff
- LVS SignOff - LVS SignOff
- PostPnR function simulation - PostPnR functional simulation

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 80 KiB

After

Width:  |  Height:  |  Size: 66 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 66 KiB

After

Width:  |  Height:  |  Size: 46 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 122 KiB

After

Width:  |  Height:  |  Size: 135 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 118 KiB

After

Width:  |  Height:  |  Size: 128 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 92 KiB

After

Width:  |  Height:  |  Size: 86 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 79 KiB

After

Width:  |  Height:  |  Size: 63 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 78 KiB

After

Width:  |  Height:  |  Size: 58 KiB

BIN
FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 96 KiB

After

Width:  |  Height:  |  Size: 85 KiB

28095
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v
View File

File diff suppressed because it is too large Load Diff

BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

21
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef
View File

@ -7,18 +7,6 @@ END UNITS
MANUFACTURINGGRID 0.005 ; MANUFACTURINGGRID 0.005 ;
LAYER nwell
TYPE MASTERSLICE ;
END nwell
LAYER pwell
TYPE MASTERSLICE ;
END pwell
LAYER fieldpoly
TYPE MASTERSLICE ;
END fieldpoly
LAYER li1 LAYER li1
TYPE ROUTING ; TYPE ROUTING ;
DIRECTION VERTICAL ; DIRECTION VERTICAL ;
@ -81,13 +69,13 @@ LAYER met5
WIDTH 1.6 ; WIDTH 1.6 ;
END met5 END met5
LAYER diff LAYER nwell
TYPE MASTERSLICE ; TYPE MASTERSLICE ;
END diff END nwell
LAYER licon1 LAYER pwell
TYPE MASTERSLICE ; TYPE MASTERSLICE ;
END licon1 END pwell
VIA L1M1_PR VIA L1M1_PR
LAYER li1 ; LAYER li1 ;
@ -352,6 +340,7 @@ END M4M5_PR_C
SITE unit SITE unit
CLASS CORE ; CLASS CORE ;
SYMMETRY Y ;
SIZE 0.46 BY 2.72 ; SIZE 0.46 BY 2.72 ;
END unit END unit

198945
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v
View File

File diff suppressed because it is too large Load Diff

BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

27521
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v
View File

File diff suppressed because it is too large Load Diff

39
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv
View File

@ -1,21 +1,18 @@
Module Util Area Sites Insts Std. Cells | Module | Util| Area| Sites| Insts| Std_Cells
===================================================================== |--------------------|----------|-----------------|-------|-------|-------
sb_0__0_ 35.3 6606.336000 5280 1 90 | sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85
sb_0__1_ 59.65 7687.372800 6144 1 124 | sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116
sb_0__2_ 24.24 6606.336000 5280 1 95 | sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85
sb_1__0_ 73.54 7807.488000 6240 1 131 | sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125
sb_1__1_ 82.56 8888.524800 7104 1 125 | sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117
sb_1__2_ 65.87 7807.488000 6240 1 135 | sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136
sb_2__0_ 56.5 6606.336000 5280 1 88 | sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94
sb_2__1_ 69.43 7687.372800 6144 1 129 | sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123
sb_2__2_ 42.06 6606.336000 5280 1 87 | sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95
cbx_1__0_ 81.3 5044.838400 4032 2 79 | cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130
cbx_1__1_ 80.58 5044.838400 4032 2 86 | cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86
cbx_1__2_ 27.26 5044.838400 4032 2 97 | cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82
cby_0__1_ 31.0 5044.838400 4032 2 99 | cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109
cby_1__1_ 82.17 5044.838400 4032 4 85 | cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88
grid_clb_1__1_ 74.63 12411.904000 9920 4 42 | cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38
grid_io_bottom_1__0_ 8.85 1681.612800 1344 2 7 | grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56
grid_io_left_0__1_ 7.59 1401.344000 1120 2 5
grid_io_right_3__1_ 8.39 1401.344000 1120 2 6
grid_io_top_1__3_ 8.11 1681.612800 1344 2 6

Can't render this file because it has a wrong number of fields in line 2.

28
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt
View File

@ -6,7 +6,7 @@ Report : clock timing
-setup -setup
Design : fpga_core Design : fpga_core
Version: P-2019.03-SP4 Version: P-2019.03-SP4
Date : Tue Oct 27 15:48:59 2020 Date : Fri Nov 6 22:19:36 2020
**************************************** ****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency --- --- Latency ---
Clock Pin Trans Source Offset Network Total Corner Clock Pin Trans Source Offset Network Total Corner
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.138 0.000 -- 0.084 0.084 rp-+ nominal grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.061 0.000 -- 0.039 0.039 rp-+ nominal
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
Mode: full_chip Mode: full_chip
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency --- --- Latency ---
Clock Pin Trans Source Offset Network Total Corner Clock Pin Trans Source Offset Network Total Corner
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
grid_clb_1__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxbp_1_1_/CLK 3.437 0.000 -- 5.205 5.205 rp-+ nominal grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.187 0.000 -- 5.545 5.545 rp-+ nominal
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
**************************************** ****************************************
Report : clock timing Report : clock timing
@ -34,7 +34,7 @@ Report : clock timing
-setup -setup
Design : fpga_core Design : fpga_core
Version: P-2019.03-SP4 Version: P-2019.03-SP4
Date : Tue Oct 27 15:48:59 2020 Date : Fri Nov 6 22:19:36 2020
**************************************** ****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner Clock Pin Latency CRP Skew Corner
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.083 rp-+ nominal grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.032 rp-+ nominal
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.051 0.000 0.032 rp-+ nominal grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.020 0.000 0.011 rp-+ nominal
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner Clock Pin Latency CRP Skew Corner
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 4.674 rp-+ nominal sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 5.061 rp-+ nominal
cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 2.007 0.000 2.666 rp-+ nominal cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.276 0.000 1.785 rp-+ nominal
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -63,13 +63,19 @@ Report : global timing
-format { narrow } -format { narrow }
Design : fpga_core Design : fpga_core
Version: P-2019.03-SP4 Version: P-2019.03-SP4
Date : Tue Oct 27 15:48:59 2020 Date : Fri Nov 6 22:19:36 2020
**************************************** ****************************************
No setup violations found. No setup violations found.
No hold violations found. Hold violations
--------------------------------------------------------------
Total reg->reg in->reg reg->out in->out
--------------------------------------------------------------
WNS -0.632 -0.632 0.000 0.000 0.000
TNS -0.750 -0.750 0.000 0.000 0.000
NUM 2 2 0 0 0
--------------------------------------------------------------
1 1

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__2__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cby_0__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cby_1__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds (Stored with Git LFS) Normal file
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_0__0__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_0__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_1__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_1__2__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_2__0__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_2__1__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds (Stored with Git LFS)
View File

Binary file not shown.

864
FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

496
FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

550
FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

421
FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

497
FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

1802
FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef Normal file
View File

File diff suppressed because it is too large Load Diff

487
FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

585
FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

460
FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

815
FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

893
FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

663
FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

546
FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

771
FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

589
FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef
View File

File diff suppressed because it is too large Load Diff

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef (Stored with Git LFS) Normal file
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

BIN
FPGA22_HIER_SKY_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef (Stored with Git LFS)
View File

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More