From 31a73a42baca31af9d26268bb33299bd9ddf1b5f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 6 Nov 2020 22:35:31 -0700 Subject: [PATCH] Updated design with new architecure and merged grid_io --- .gitignore | 2 + .../SRC/InstancesMap.txt | 1 + .../SRC/fabric_netlists.v | 15 +- .../FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v | 2757 +- .../FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v | 1938 +- .../FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v | 414 +- .../SRC/lb/grid_io_bottom.v | 137 +- .../SRC/lb/grid_io_left.v | 32 +- .../SRC/lb/grid_io_right.v | 32 +- .../SRC/lb/grid_io_top.v | 32 +- .../SRC/lb/logical_tile_clb_mode_clb_.v | 192 +- .../lb/logical_tile_clb_mode_default__fle.v | 24 +- ..._mode_default__fle_mode_physical__fabric.v | 16 +- ...e_mode_physical__fabric_mode_default__ff.v | 2 +- .../SRC/lb/logical_tile_io_mode_io_.v | 22 +- .../lb/logical_tile_io_mode_physical__iopad.v | 40 +- .../SRC/routing/cbx_1__0_.v | 782 +- .../SRC/routing/cbx_1__1_.v | 899 +- .../SRC/routing/cbx_1__2_.v | 718 +- .../SRC/routing/cby_0__1_.v | 331 +- .../SRC/routing/cby_1__1_.v | 905 +- .../SRC/routing/cby_2__1_.v | 502 + .../SRC/routing/sb_0__0_.v | 890 +- .../SRC/routing/sb_0__1_.v | 1376 +- .../SRC/routing/sb_0__2_.v | 887 +- .../SRC/routing/sb_1__0_.v | 1511 +- .../SRC/routing/sb_1__1_.v | 1461 +- .../SRC/routing/sb_1__2_.v | 1481 +- .../SRC/routing/sb_2__0_.v | 1426 +- .../SRC/routing/sb_2__1_.v | 1436 +- .../SRC/routing/sb_2__2_.v | 1300 +- .../SRC/sub_module/digital_io_hd.v | 63 + .../SRC/sub_module/memories.v | 629 +- .../SRC/sub_module/muxes.v | 1050 +- .../SRC/top_autocheck_top_tb.v | 472 +- .../SRC/top_formal_random_top_tb.v | 4 +- .../SRC/top_top_formal_verification.v | 1309 +- .../TESTBENCH/top/fabric_bitstream.bit | 2 +- .../TESTBENCH/top/fabric_bitstream.xml | 4214 +- .../top/fabric_indepenent_bitstream.xml | 5135 +- .../FPGA22_HIER_SKY_Verilog/openfpgashell.log | 586 +- .../FPGA22_HIER_SKY_task/arch/fabric_key.xml | 68 +- .../arch/openfpga_arch.xml | 30 +- .../FPGA22_HIER_SKY_task/arch/vpr_arch.xml | 250 +- .../sc_verilog/digital_io_hd.v | 63 + FPGA22_HIER_SKY_PNR/README.md | 11 +- .../fpga_core/Screenshots/ProgClockTree.png | Bin 82019 -> 67614 bytes .../fpga_core/Screenshots/clockTree.png | Bin 67658 -> 47462 bytes .../Screenshots/met1_utilization.png | Bin 125306 -> 138519 bytes .../Screenshots/met2_utilization.png | Bin 120623 -> 131156 bytes .../Screenshots/met3_utilization.png | Bin 94720 -> 87869 bytes .../Screenshots/met4_utilization.png | Bin 80777 -> 64310 bytes .../fpga_core/Screenshots/power_contacts.png | Bin 79525 -> 59178 bytes .../fpga_core/Screenshots/utilization.png | Bin 97896 -> 86804 bytes .../fpga_core/fpga_core_icv_in_design.fm.v | 28191 +- .../fpga_core/fpga_core_icv_in_design.gds | 4 +- .../fpga_core/fpga_core_icv_in_design.lef | 21 +- .../fpga_core/fpga_core_icv_in_design.lvs.v | 199049 ++++----------- .../fpga_core_icv_in_design.nominal_25.spef | 4 +- .../fpga_core/fpga_core_icv_in_design.pt.v | 27625 +- .../rpts_icc2/module_utilization.tsv | 39 +- .../fpga_core/rpts_icc2/timing_reports.txt | 28 +- .../modules/gds/cbx_1__0__icv_in_design.gds | 4 +- .../modules/gds/cbx_1__1__icv_in_design.gds | 4 +- .../modules/gds/cbx_1__2__icv_in_design.gds | 4 +- .../modules/gds/cby_0__1__icv_in_design.gds | 4 +- .../modules/gds/cby_1__1__icv_in_design.gds | 4 +- .../modules/gds/cby_2__1__icv_in_design.gds | 3 + .../modules/gds/sb_0__0__icv_in_design.gds | 4 +- .../modules/gds/sb_0__1__icv_in_design.gds | 4 +- .../modules/gds/sb_0__2__icv_in_design.gds | 4 +- .../modules/gds/sb_1__0__icv_in_design.gds | 4 +- .../modules/gds/sb_1__1__icv_in_design.gds | 4 +- .../modules/gds/sb_1__2__icv_in_design.gds | 4 +- .../modules/gds/sb_2__0__icv_in_design.gds | 4 +- .../modules/gds/sb_2__1__icv_in_design.gds | 4 +- .../modules/gds/sb_2__2__icv_in_design.gds | 4 +- .../modules/lef/cbx_1__0__icv_in_design.lef | 864 +- .../modules/lef/cbx_1__1__icv_in_design.lef | 496 +- .../modules/lef/cbx_1__2__icv_in_design.lef | 550 +- .../modules/lef/cby_0__1__icv_in_design.lef | 421 +- .../modules/lef/cby_1__1__icv_in_design.lef | 497 +- .../modules/lef/cby_2__1__icv_in_design.lef | 1802 + .../modules/lef/sb_0__0__icv_in_design.lef | 487 +- .../modules/lef/sb_0__1__icv_in_design.lef | 585 +- .../modules/lef/sb_0__2__icv_in_design.lef | 460 +- .../modules/lef/sb_1__0__icv_in_design.lef | 815 +- .../modules/lef/sb_1__1__icv_in_design.lef | 893 +- .../modules/lef/sb_1__2__icv_in_design.lef | 663 +- .../modules/lef/sb_2__0__icv_in_design.lef | 546 +- .../modules/lef/sb_2__1__icv_in_design.lef | 771 +- .../modules/lef/sb_2__2__icv_in_design.lef | 589 +- .../cbx_1__0__icv_in_design.nominal_25.spef | 4 +- .../cbx_1__1__icv_in_design.nominal_25.spef | 4 +- .../cbx_1__2__icv_in_design.nominal_25.spef | 4 +- .../cby_0__1__icv_in_design.nominal_25.spef | 4 +- .../cby_1__1__icv_in_design.nominal_25.spef | 4 +- .../cby_2__1__icv_in_design.nominal_25.spef | 3 + .../sb_0__0__icv_in_design.nominal_25.spef | 4 +- .../sb_0__1__icv_in_design.nominal_25.spef | 4 +- .../sb_0__2__icv_in_design.nominal_25.spef | 4 +- .../sb_1__0__icv_in_design.nominal_25.spef | 4 +- .../sb_1__1__icv_in_design.nominal_25.spef | 4 +- .../sb_1__2__icv_in_design.nominal_25.spef | 4 +- .../sb_2__0__icv_in_design.nominal_25.spef | 4 +- .../sb_2__1__icv_in_design.nominal_25.spef | 4 +- .../sb_2__2__icv_in_design.nominal_25.spef | 4 +- .../verilog/cbx_1__0__icv_in_design.fm.v | 2081 +- .../verilog/cbx_1__0__icv_in_design.lvs.v | 3014 +- .../verilog/cbx_1__0__icv_in_design.pt.v | 2080 +- .../verilog/cbx_1__1__icv_in_design.fm.v | 779 +- .../verilog/cbx_1__1__icv_in_design.lvs.v | 1317 +- .../verilog/cbx_1__1__icv_in_design.pt.v | 855 +- .../verilog/cbx_1__2__icv_in_design.fm.v | 1897 +- .../verilog/cbx_1__2__icv_in_design.lvs.v | 2956 +- .../verilog/cbx_1__2__icv_in_design.pt.v | 1781 +- .../verilog/cby_0__1__icv_in_design.fm.v | 633 +- .../verilog/cby_0__1__icv_in_design.lvs.v | 1411 +- .../verilog/cby_0__1__icv_in_design.pt.v | 626 +- .../verilog/cby_1__1__icv_in_design.fm.v | 913 +- .../verilog/cby_1__1__icv_in_design.lvs.v | 1796 +- .../verilog/cby_1__1__icv_in_design.pt.v | 1280 +- .../verilog/cby_2__1__icv_in_design.fm.v | 1778 + .../verilog/cby_2__1__icv_in_design.lvs.v | 2600 + .../verilog/cby_2__1__icv_in_design.pt.v | 1642 + .../verilog/sb_0__0__icv_in_design.fm.v | 1445 +- .../verilog/sb_0__0__icv_in_design.lvs.v | 2748 +- .../verilog/sb_0__0__icv_in_design.pt.v | 1391 +- .../verilog/sb_0__1__icv_in_design.fm.v | 715 +- .../verilog/sb_0__1__icv_in_design.lvs.v | 2072 +- .../verilog/sb_0__1__icv_in_design.pt.v | 680 +- .../verilog/sb_0__2__icv_in_design.fm.v | 1444 +- .../verilog/sb_0__2__icv_in_design.lvs.v | 2663 +- .../verilog/sb_0__2__icv_in_design.pt.v | 1294 +- .../verilog/sb_1__0__icv_in_design.fm.v | 2012 +- .../verilog/sb_1__0__icv_in_design.lvs.v | 3360 +- .../verilog/sb_1__0__icv_in_design.pt.v | 2037 +- .../verilog/sb_1__1__icv_in_design.fm.v | 491 +- .../verilog/sb_1__1__icv_in_design.lvs.v | 1209 +- .../verilog/sb_1__1__icv_in_design.pt.v | 491 +- .../verilog/sb_1__2__icv_in_design.fm.v | 3562 +- .../verilog/sb_1__2__icv_in_design.lvs.v | 5194 +- .../verilog/sb_1__2__icv_in_design.pt.v | 3330 +- .../verilog/sb_2__0__icv_in_design.fm.v | 1907 +- .../verilog/sb_2__0__icv_in_design.lvs.v | 3399 +- .../verilog/sb_2__0__icv_in_design.pt.v | 1735 +- .../verilog/sb_2__1__icv_in_design.fm.v | 921 +- .../verilog/sb_2__1__icv_in_design.lvs.v | 2067 +- .../verilog/sb_2__1__icv_in_design.pt.v | 875 +- .../verilog/sb_2__2__icv_in_design.fm.v | 1617 +- .../verilog/sb_2__2__icv_in_design.lvs.v | 2892 +- .../verilog/sb_2__2__icv_in_design.pt.v | 1346 +- 152 files changed, 155135 insertions(+), 228166 deletions(-) create mode 100644 FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt create mode 100644 FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v create mode 100644 FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v create mode 100644 FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds create mode 100644 FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef create mode 100644 FPGA22_HIER_SKY_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v diff --git a/.gitignore b/.gitignore index fa7bd55..7c8c7ac 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,5 @@ **/*_task/run001 **/*_task/latest **/*_task/skywater +**/*_Verilog/SRC_Skeleton +**/*_Verilog/SRCBackup diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt new file mode 100644 index 0000000..b431eb5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt @@ -0,0 +1 @@ +{"grid_clb": ["grid_clb_1__1_", "grid_clb_1__2_", "grid_clb_2__1_", "grid_clb_2__2_"], "grid_io_top": ["grid_io_top_1__3_", "grid_io_top_2__3_"], "grid_io_right": ["grid_io_right_3__1_", "grid_io_right_3__2_"], "grid_io_bottom": ["grid_io_bottom_1__0_", "grid_io_bottom_2__0_"], "grid_io_left": ["grid_io_left_0__1_", "grid_io_left_0__2_"], "sb_0__0_": ["sb_0__0_"], "sb_0__1_": ["sb_0__1_"], "sb_0__2_": ["sb_0__2_"], "sb_1__0_": ["sb_1__0_"], "sb_1__1_": ["sb_1__1_"], "sb_1__2_": ["sb_1__2_"], "sb_2__0_": ["sb_2__0_"], "sb_2__1_": ["sb_2__1_"], "sb_2__2_": ["sb_2__2_"], "cbx_1__0_": ["cbx_1__0_", "cbx_2__0_"], "cbx_1__1_": ["cbx_1__1_", "cbx_2__1_"], "cbx_1__2_": ["cbx_1__2_", "cbx_2__2_"], "cby_0__1_": ["cby_0__1_", "cby_0__2_"], "cby_1__1_": ["cby_1__1_", "cby_1__2_"], "cby_2__1_": ["cby_2__1_", "cby_2__2_"], "direct_interc": ["direct_interc_0_", "direct_interc_1_", "direct_interc_2_", "direct_interc_3_", "direct_interc_4_", "direct_interc_5_"]} \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v index 523cc86..d6db793 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v @@ -18,9 +18,9 @@ `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/std_cell_extract.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" // `include "./SRC/sub_module/inv_buf_passgate.v" `include "./SRC/sub_module/arch_encoder.v" @@ -39,10 +39,10 @@ `include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" `include "./SRC/lb/logical_tile_clb_mode_default__fle.v" `include "./SRC/lb/logical_tile_clb_mode_clb_.v" -`include "./SRC/lb/grid_io_top.v" -`include "./SRC/lb/grid_io_right.v" -`include "./SRC/lb/grid_io_bottom.v" -`include "./SRC/lb/grid_io_left.v" +`include "./SRC/lb/grid_io_top_top.v" +`include "./SRC/lb/grid_io_right_right.v" +`include "./SRC/lb/grid_io_bottom_bottom.v" +`include "./SRC/lb/grid_io_left_left.v" `include "./SRC/lb/grid_clb.v" // @@ -60,6 +60,7 @@ `include "./SRC/routing/cbx_1__2_.v" `include "./SRC/routing/cby_0__1_.v" `include "./SRC/routing/cby_1__1_.v" +`include "./SRC/routing/cby_2__1_.v" // `include "./SRC/fpga_top.v" diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v index e5e1c6b..49d1358 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v @@ -1,1347 +1,1504 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module fpga_core(prog_clk, - Test_en, - clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - ccff_head, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -output [0:7] gfpga_pad_GPIO_A; -// -output [0:7] gfpga_pad_GPIO_IE; -// -output [0:7] gfpga_pad_GPIO_OE; -// -inout [0:7] gfpga_pad_GPIO_Y; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; - -// -// -// -// +module fpga_core +( + input [0:0] prog_clk, + input [0:0] Test_en, + input [0:0] clk, + input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] ccff_head, + output [0:0] ccff_tail, + input sc_head, + output sc_tail +); + + wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__0__0_ccff_tail; + wire [0:19] cbx_1__0__0_chanx_left_out; + wire [0:19] cbx_1__0__0_chanx_right_out; + wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__0__1_ccff_tail; + wire [0:19] cbx_1__0__1_chanx_left_out; + wire [0:19] cbx_1__0__1_chanx_right_out; + wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; + wire [0:0] cbx_1__1__0_ccff_tail; + wire [0:19] cbx_1__1__0_chanx_left_out; + wire [0:19] cbx_1__1__0_chanx_right_out; + wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; + wire [0:0] cbx_1__1__1_ccff_tail; + wire [0:19] cbx_1__1__1_chanx_left_out; + wire [0:19] cbx_1__1__1_chanx_right_out; + wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; + wire [0:0] cbx_1__2__0_ccff_tail; + wire [0:19] cbx_1__2__0_chanx_left_out; + wire [0:19] cbx_1__2__0_chanx_right_out; + wire [0:0] cbx_1__2__0_top_grid_pin_0_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; + wire [0:0] cbx_1__2__1_ccff_tail; + wire [0:19] cbx_1__2__1_chanx_left_out; + wire [0:19] cbx_1__2__1_chanx_right_out; + wire [0:0] cbx_1__2__1_top_grid_pin_0_; + wire [0:0] cby_0__1__0_ccff_tail; + wire [0:19] cby_0__1__0_chany_bottom_out; + wire [0:19] cby_0__1__0_chany_top_out; + wire [0:0] cby_0__1__0_left_grid_pin_0_; + wire [0:0] cby_0__1__1_ccff_tail; + wire [0:19] cby_0__1__1_chany_bottom_out; + wire [0:19] cby_0__1__1_chany_top_out; + wire [0:0] cby_0__1__1_left_grid_pin_0_; + wire [0:0] cby_1__1__0_ccff_tail; + wire [0:19] cby_1__1__0_chany_bottom_out; + wire [0:19] cby_1__1__0_chany_top_out; + wire [0:0] cby_1__1__0_left_grid_pin_16_; + wire [0:0] cby_1__1__0_left_grid_pin_17_; + wire [0:0] cby_1__1__0_left_grid_pin_18_; + wire [0:0] cby_1__1__0_left_grid_pin_19_; + wire [0:0] cby_1__1__0_left_grid_pin_20_; + wire [0:0] cby_1__1__0_left_grid_pin_21_; + wire [0:0] cby_1__1__0_left_grid_pin_22_; + wire [0:0] cby_1__1__0_left_grid_pin_23_; + wire [0:0] cby_1__1__0_left_grid_pin_24_; + wire [0:0] cby_1__1__0_left_grid_pin_25_; + wire [0:0] cby_1__1__0_left_grid_pin_26_; + wire [0:0] cby_1__1__0_left_grid_pin_27_; + wire [0:0] cby_1__1__0_left_grid_pin_28_; + wire [0:0] cby_1__1__0_left_grid_pin_29_; + wire [0:0] cby_1__1__0_left_grid_pin_30_; + wire [0:0] cby_1__1__0_left_grid_pin_31_; + wire [0:0] cby_1__1__1_ccff_tail; + wire [0:19] cby_1__1__1_chany_bottom_out; + wire [0:19] cby_1__1__1_chany_top_out; + wire [0:0] cby_1__1__1_left_grid_pin_16_; + wire [0:0] cby_1__1__1_left_grid_pin_17_; + wire [0:0] cby_1__1__1_left_grid_pin_18_; + wire [0:0] cby_1__1__1_left_grid_pin_19_; + wire [0:0] cby_1__1__1_left_grid_pin_20_; + wire [0:0] cby_1__1__1_left_grid_pin_21_; + wire [0:0] cby_1__1__1_left_grid_pin_22_; + wire [0:0] cby_1__1__1_left_grid_pin_23_; + wire [0:0] cby_1__1__1_left_grid_pin_24_; + wire [0:0] cby_1__1__1_left_grid_pin_25_; + wire [0:0] cby_1__1__1_left_grid_pin_26_; + wire [0:0] cby_1__1__1_left_grid_pin_27_; + wire [0:0] cby_1__1__1_left_grid_pin_28_; + wire [0:0] cby_1__1__1_left_grid_pin_29_; + wire [0:0] cby_1__1__1_left_grid_pin_30_; + wire [0:0] cby_1__1__1_left_grid_pin_31_; + wire [0:0] cby_2__1__0_ccff_tail; + wire [0:19] cby_2__1__0_chany_bottom_out; + wire [0:19] cby_2__1__0_chany_top_out; + wire [0:0] cby_2__1__0_left_grid_pin_16_; + wire [0:0] cby_2__1__0_left_grid_pin_17_; + wire [0:0] cby_2__1__0_left_grid_pin_18_; + wire [0:0] cby_2__1__0_left_grid_pin_19_; + wire [0:0] cby_2__1__0_left_grid_pin_20_; + wire [0:0] cby_2__1__0_left_grid_pin_21_; + wire [0:0] cby_2__1__0_left_grid_pin_22_; + wire [0:0] cby_2__1__0_left_grid_pin_23_; + wire [0:0] cby_2__1__0_left_grid_pin_24_; + wire [0:0] cby_2__1__0_left_grid_pin_25_; + wire [0:0] cby_2__1__0_left_grid_pin_26_; + wire [0:0] cby_2__1__0_left_grid_pin_27_; + wire [0:0] cby_2__1__0_left_grid_pin_28_; + wire [0:0] cby_2__1__0_left_grid_pin_29_; + wire [0:0] cby_2__1__0_left_grid_pin_30_; + wire [0:0] cby_2__1__0_left_grid_pin_31_; + wire [0:0] cby_2__1__0_right_grid_pin_0_; + wire [0:0] cby_2__1__1_ccff_tail; + wire [0:19] cby_2__1__1_chany_bottom_out; + wire [0:19] cby_2__1__1_chany_top_out; + wire [0:0] cby_2__1__1_left_grid_pin_16_; + wire [0:0] cby_2__1__1_left_grid_pin_17_; + wire [0:0] cby_2__1__1_left_grid_pin_18_; + wire [0:0] cby_2__1__1_left_grid_pin_19_; + wire [0:0] cby_2__1__1_left_grid_pin_20_; + wire [0:0] cby_2__1__1_left_grid_pin_21_; + wire [0:0] cby_2__1__1_left_grid_pin_22_; + wire [0:0] cby_2__1__1_left_grid_pin_23_; + wire [0:0] cby_2__1__1_left_grid_pin_24_; + wire [0:0] cby_2__1__1_left_grid_pin_25_; + wire [0:0] cby_2__1__1_left_grid_pin_26_; + wire [0:0] cby_2__1__1_left_grid_pin_27_; + wire [0:0] cby_2__1__1_left_grid_pin_28_; + wire [0:0] cby_2__1__1_left_grid_pin_29_; + wire [0:0] cby_2__1__1_left_grid_pin_30_; + wire [0:0] cby_2__1__1_left_grid_pin_31_; + wire [0:0] cby_2__1__1_right_grid_pin_0_; + wire [0:0] direct_interc_0_out; + wire [0:0] direct_interc_1_out; + wire [0:0] direct_interc_2_out; + wire [0:0] direct_interc_3_out; + wire [0:0] direct_interc_4_out; + wire [0:0] direct_interc_5_out; + wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_0_ccff_tail; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; + wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; + wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_1_ccff_tail; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_2_ccff_tail; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_3_ccff_tail; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_io_bottom_0_ccff_tail; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper; + wire [0:0] grid_io_bottom_1_ccff_tail; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper; + wire [0:0] grid_io_left_0_ccff_tail; + wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_left_1_ccff_tail; + wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_right_0_ccff_tail; + wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_right_1_ccff_tail; + wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_0_ccff_tail; + wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_1_ccff_tail; + wire [0:19] sb_0__0__0_chanx_right_out; + wire [0:19] sb_0__0__0_chany_top_out; + wire [0:0] sb_0__1__0_ccff_tail; + wire [0:19] sb_0__1__0_chanx_right_out; + wire [0:19] sb_0__1__0_chany_bottom_out; + wire [0:19] sb_0__1__0_chany_top_out; + wire [0:0] sb_0__2__0_ccff_tail; + wire [0:19] sb_0__2__0_chanx_right_out; + wire [0:19] sb_0__2__0_chany_bottom_out; + wire [0:0] sb_1__0__0_ccff_tail; + wire [0:19] sb_1__0__0_chanx_left_out; + wire [0:19] sb_1__0__0_chanx_right_out; + wire [0:19] sb_1__0__0_chany_top_out; + wire [0:0] sb_1__1__0_ccff_tail; + wire [0:19] sb_1__1__0_chanx_left_out; + wire [0:19] sb_1__1__0_chanx_right_out; + wire [0:19] sb_1__1__0_chany_bottom_out; + wire [0:19] sb_1__1__0_chany_top_out; + wire [0:0] sb_1__2__0_ccff_tail; + wire [0:19] sb_1__2__0_chanx_left_out; + wire [0:19] sb_1__2__0_chanx_right_out; + wire [0:19] sb_1__2__0_chany_bottom_out; + wire [0:0] sb_2__0__0_ccff_tail; + wire [0:19] sb_2__0__0_chanx_left_out; + wire [0:19] sb_2__0__0_chany_top_out; + wire [0:0] sb_2__1__0_ccff_tail; + wire [0:19] sb_2__1__0_chanx_left_out; + wire [0:19] sb_2__1__0_chany_bottom_out; + wire [0:19] sb_2__1__0_chany_top_out; + wire [0:0] sb_2__2__0_ccff_tail; + wire [0:19] sb_2__2__0_chanx_left_out; + wire [0:19] sb_2__2__0_chany_bottom_out; + wire [1:0] UNCONN; + wire [2:0] sc_out_wires; + wire [2:0] sc_in_wires; + wire [12:0] scff_Wires; + + grid_clb + grid_clb_1__1_ + ( + .SC_OUT_BOT(scff_Wires[5]), + .SC_IN_TOP(scff_Wires[3]), + .top_width_0_height_0__pin_33_(sc_in_wires[0]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), + .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_0_ccff_tail[0]) + ); -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__0_ccff_tail; -wire [0:19] cbx_1__0__0_chanx_left_out; -wire [0:19] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__0__0_top_grid_pin_16_; -wire [0:0] cbx_1__0__0_top_grid_pin_17_; -wire [0:0] cbx_1__0__0_top_grid_pin_18_; -wire [0:0] cbx_1__0__0_top_grid_pin_19_; -wire [0:0] cbx_1__0__0_top_grid_pin_20_; -wire [0:0] cbx_1__0__0_top_grid_pin_21_; -wire [0:0] cbx_1__0__0_top_grid_pin_22_; -wire [0:0] cbx_1__0__0_top_grid_pin_23_; -wire [0:0] cbx_1__0__0_top_grid_pin_24_; -wire [0:0] cbx_1__0__0_top_grid_pin_25_; -wire [0:0] cbx_1__0__0_top_grid_pin_26_; -wire [0:0] cbx_1__0__0_top_grid_pin_27_; -wire [0:0] cbx_1__0__0_top_grid_pin_28_; -wire [0:0] cbx_1__0__0_top_grid_pin_29_; -wire [0:0] cbx_1__0__0_top_grid_pin_30_; -wire [0:0] cbx_1__0__0_top_grid_pin_31_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__1_ccff_tail; -wire [0:19] cbx_1__0__1_chanx_left_out; -wire [0:19] cbx_1__0__1_chanx_right_out; -wire [0:0] cbx_1__0__1_top_grid_pin_16_; -wire [0:0] cbx_1__0__1_top_grid_pin_17_; -wire [0:0] cbx_1__0__1_top_grid_pin_18_; -wire [0:0] cbx_1__0__1_top_grid_pin_19_; -wire [0:0] cbx_1__0__1_top_grid_pin_20_; -wire [0:0] cbx_1__0__1_top_grid_pin_21_; -wire [0:0] cbx_1__0__1_top_grid_pin_22_; -wire [0:0] cbx_1__0__1_top_grid_pin_23_; -wire [0:0] cbx_1__0__1_top_grid_pin_24_; -wire [0:0] cbx_1__0__1_top_grid_pin_25_; -wire [0:0] cbx_1__0__1_top_grid_pin_26_; -wire [0:0] cbx_1__0__1_top_grid_pin_27_; -wire [0:0] cbx_1__0__1_top_grid_pin_28_; -wire [0:0] cbx_1__0__1_top_grid_pin_29_; -wire [0:0] cbx_1__0__1_top_grid_pin_30_; -wire [0:0] cbx_1__0__1_top_grid_pin_31_; -wire [0:0] cbx_1__1__0_ccff_tail; -wire [0:19] cbx_1__1__0_chanx_left_out; -wire [0:19] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__0_top_grid_pin_16_; -wire [0:0] cbx_1__1__0_top_grid_pin_17_; -wire [0:0] cbx_1__1__0_top_grid_pin_18_; -wire [0:0] cbx_1__1__0_top_grid_pin_19_; -wire [0:0] cbx_1__1__0_top_grid_pin_20_; -wire [0:0] cbx_1__1__0_top_grid_pin_21_; -wire [0:0] cbx_1__1__0_top_grid_pin_22_; -wire [0:0] cbx_1__1__0_top_grid_pin_23_; -wire [0:0] cbx_1__1__0_top_grid_pin_24_; -wire [0:0] cbx_1__1__0_top_grid_pin_25_; -wire [0:0] cbx_1__1__0_top_grid_pin_26_; -wire [0:0] cbx_1__1__0_top_grid_pin_27_; -wire [0:0] cbx_1__1__0_top_grid_pin_28_; -wire [0:0] cbx_1__1__0_top_grid_pin_29_; -wire [0:0] cbx_1__1__0_top_grid_pin_30_; -wire [0:0] cbx_1__1__0_top_grid_pin_31_; -wire [0:0] cbx_1__1__1_ccff_tail; -wire [0:19] cbx_1__1__1_chanx_left_out; -wire [0:19] cbx_1__1__1_chanx_right_out; -wire [0:0] cbx_1__1__1_top_grid_pin_16_; -wire [0:0] cbx_1__1__1_top_grid_pin_17_; -wire [0:0] cbx_1__1__1_top_grid_pin_18_; -wire [0:0] cbx_1__1__1_top_grid_pin_19_; -wire [0:0] cbx_1__1__1_top_grid_pin_20_; -wire [0:0] cbx_1__1__1_top_grid_pin_21_; -wire [0:0] cbx_1__1__1_top_grid_pin_22_; -wire [0:0] cbx_1__1__1_top_grid_pin_23_; -wire [0:0] cbx_1__1__1_top_grid_pin_24_; -wire [0:0] cbx_1__1__1_top_grid_pin_25_; -wire [0:0] cbx_1__1__1_top_grid_pin_26_; -wire [0:0] cbx_1__1__1_top_grid_pin_27_; -wire [0:0] cbx_1__1__1_top_grid_pin_28_; -wire [0:0] cbx_1__1__1_top_grid_pin_29_; -wire [0:0] cbx_1__1__1_top_grid_pin_30_; -wire [0:0] cbx_1__1__1_top_grid_pin_31_; -wire [0:0] cbx_1__2__0_ccff_tail; -wire [0:19] cbx_1__2__0_chanx_left_out; -wire [0:19] cbx_1__2__0_chanx_right_out; -wire [0:0] cbx_1__2__0_top_grid_pin_0_; -wire [0:0] cbx_1__2__1_ccff_tail; -wire [0:19] cbx_1__2__1_chanx_left_out; -wire [0:19] cbx_1__2__1_chanx_right_out; -wire [0:0] cbx_1__2__1_top_grid_pin_0_; -wire [0:0] cby_0__1__0_ccff_tail; -wire [0:19] cby_0__1__0_chany_bottom_out; -wire [0:19] cby_0__1__0_chany_top_out; -wire [0:0] cby_0__1__0_left_grid_pin_0_; -wire [0:0] cby_0__1__0_right_grid_pin_52_; -wire [0:0] cby_0__1__1_ccff_tail; -wire [0:19] cby_0__1__1_chany_bottom_out; -wire [0:19] cby_0__1__1_chany_top_out; -wire [0:0] cby_0__1__1_left_grid_pin_0_; -wire [0:0] cby_0__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__0_ccff_tail; -wire [0:19] cby_1__1__0_chany_bottom_out; -wire [0:19] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_pin_0_; -wire [0:0] cby_1__1__0_left_grid_pin_10_; -wire [0:0] cby_1__1__0_left_grid_pin_11_; -wire [0:0] cby_1__1__0_left_grid_pin_12_; -wire [0:0] cby_1__1__0_left_grid_pin_13_; -wire [0:0] cby_1__1__0_left_grid_pin_14_; -wire [0:0] cby_1__1__0_left_grid_pin_15_; -wire [0:0] cby_1__1__0_left_grid_pin_1_; -wire [0:0] cby_1__1__0_left_grid_pin_2_; -wire [0:0] cby_1__1__0_left_grid_pin_3_; -wire [0:0] cby_1__1__0_left_grid_pin_4_; -wire [0:0] cby_1__1__0_left_grid_pin_5_; -wire [0:0] cby_1__1__0_left_grid_pin_6_; -wire [0:0] cby_1__1__0_left_grid_pin_7_; -wire [0:0] cby_1__1__0_left_grid_pin_8_; -wire [0:0] cby_1__1__0_left_grid_pin_9_; -wire [0:0] cby_1__1__0_right_grid_pin_52_; -wire [0:0] cby_1__1__1_ccff_tail; -wire [0:19] cby_1__1__1_chany_bottom_out; -wire [0:19] cby_1__1__1_chany_top_out; -wire [0:0] cby_1__1__1_left_grid_pin_0_; -wire [0:0] cby_1__1__1_left_grid_pin_10_; -wire [0:0] cby_1__1__1_left_grid_pin_11_; -wire [0:0] cby_1__1__1_left_grid_pin_12_; -wire [0:0] cby_1__1__1_left_grid_pin_13_; -wire [0:0] cby_1__1__1_left_grid_pin_14_; -wire [0:0] cby_1__1__1_left_grid_pin_15_; -wire [0:0] cby_1__1__1_left_grid_pin_1_; -wire [0:0] cby_1__1__1_left_grid_pin_2_; -wire [0:0] cby_1__1__1_left_grid_pin_3_; -wire [0:0] cby_1__1__1_left_grid_pin_4_; -wire [0:0] cby_1__1__1_left_grid_pin_5_; -wire [0:0] cby_1__1__1_left_grid_pin_6_; -wire [0:0] cby_1__1__1_left_grid_pin_7_; -wire [0:0] cby_1__1__1_left_grid_pin_8_; -wire [0:0] cby_1__1__1_left_grid_pin_9_; -wire [0:0] cby_1__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__2_ccff_tail; -wire [0:19] cby_1__1__2_chany_bottom_out; -wire [0:19] cby_1__1__2_chany_top_out; -wire [0:0] cby_1__1__2_left_grid_pin_0_; -wire [0:0] cby_1__1__2_left_grid_pin_10_; -wire [0:0] cby_1__1__2_left_grid_pin_11_; -wire [0:0] cby_1__1__2_left_grid_pin_12_; -wire [0:0] cby_1__1__2_left_grid_pin_13_; -wire [0:0] cby_1__1__2_left_grid_pin_14_; -wire [0:0] cby_1__1__2_left_grid_pin_15_; -wire [0:0] cby_1__1__2_left_grid_pin_1_; -wire [0:0] cby_1__1__2_left_grid_pin_2_; -wire [0:0] cby_1__1__2_left_grid_pin_3_; -wire [0:0] cby_1__1__2_left_grid_pin_4_; -wire [0:0] cby_1__1__2_left_grid_pin_5_; -wire [0:0] cby_1__1__2_left_grid_pin_6_; -wire [0:0] cby_1__1__2_left_grid_pin_7_; -wire [0:0] cby_1__1__2_left_grid_pin_8_; -wire [0:0] cby_1__1__2_left_grid_pin_9_; -wire [0:0] cby_1__1__2_right_grid_pin_52_; -wire [0:0] cby_1__1__3_ccff_tail; -wire [0:19] cby_1__1__3_chany_bottom_out; -wire [0:19] cby_1__1__3_chany_top_out; -wire [0:0] cby_1__1__3_left_grid_pin_0_; -wire [0:0] cby_1__1__3_left_grid_pin_10_; -wire [0:0] cby_1__1__3_left_grid_pin_11_; -wire [0:0] cby_1__1__3_left_grid_pin_12_; -wire [0:0] cby_1__1__3_left_grid_pin_13_; -wire [0:0] cby_1__1__3_left_grid_pin_14_; -wire [0:0] cby_1__1__3_left_grid_pin_15_; -wire [0:0] cby_1__1__3_left_grid_pin_1_; -wire [0:0] cby_1__1__3_left_grid_pin_2_; -wire [0:0] cby_1__1__3_left_grid_pin_3_; -wire [0:0] cby_1__1__3_left_grid_pin_4_; -wire [0:0] cby_1__1__3_left_grid_pin_5_; -wire [0:0] cby_1__1__3_left_grid_pin_6_; -wire [0:0] cby_1__1__3_left_grid_pin_7_; -wire [0:0] cby_1__1__3_left_grid_pin_8_; -wire [0:0] cby_1__1__3_left_grid_pin_9_; -wire [0:0] cby_1__1__3_right_grid_pin_52_; -wire [0:0] direct_interc_0_out; -wire [0:0] direct_interc_1_out; -wire [0:0] direct_interc_2_out; -wire [0:0] direct_interc_3_out; -wire [0:0] direct_interc_4_out; -wire [0:0] direct_interc_5_out; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_0_ccff_tail; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_1_ccff_tail; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_2_ccff_tail; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_3_ccff_tail; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_io_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_1_ccff_tail; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_0_ccff_tail; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_1_ccff_tail; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_0_ccff_tail; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_1_ccff_tail; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_ccff_tail; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_1_ccff_tail; -wire [0:19] sb_0__0__0_chanx_right_out; -wire [0:19] sb_0__0__0_chany_top_out; -wire [0:0] sb_0__1__0_ccff_tail; -wire [0:19] sb_0__1__0_chanx_right_out; -wire [0:19] sb_0__1__0_chany_bottom_out; -wire [0:19] sb_0__1__0_chany_top_out; -wire [0:0] sb_0__2__0_ccff_tail; -wire [0:19] sb_0__2__0_chanx_right_out; -wire [0:19] sb_0__2__0_chany_bottom_out; -wire [0:0] sb_1__0__0_ccff_tail; -wire [0:19] sb_1__0__0_chanx_left_out; -wire [0:19] sb_1__0__0_chanx_right_out; -wire [0:19] sb_1__0__0_chany_top_out; -wire [0:0] sb_1__1__0_ccff_tail; -wire [0:19] sb_1__1__0_chanx_left_out; -wire [0:19] sb_1__1__0_chanx_right_out; -wire [0:19] sb_1__1__0_chany_bottom_out; -wire [0:19] sb_1__1__0_chany_top_out; -wire [0:0] sb_1__2__0_ccff_tail; -wire [0:19] sb_1__2__0_chanx_left_out; -wire [0:19] sb_1__2__0_chanx_right_out; -wire [0:19] sb_1__2__0_chany_bottom_out; -wire [0:0] sb_2__0__0_ccff_tail; -wire [0:19] sb_2__0__0_chanx_left_out; -wire [0:19] sb_2__0__0_chany_top_out; -wire [0:0] sb_2__1__0_ccff_tail; -wire [0:19] sb_2__1__0_chanx_left_out; -wire [0:19] sb_2__1__0_chany_bottom_out; -wire [0:19] sb_2__1__0_chany_top_out; -wire [0:0] sb_2__2__0_ccff_tail; -wire [0:19] sb_2__2__0_chanx_left_out; -wire [0:19] sb_2__2__0_chany_bottom_out; + grid_clb + grid_clb_1__2_ + ( + .SC_OUT_BOT(scff_Wires[2]), + .SC_IN_TOP(scff_Wires[1]), + .bottom_width_0_height_0__pin_51_(sc_out_wires[0]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), + .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), + .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .ccff_tail(grid_clb_1_ccff_tail[0]) + ); -// -// -// -// - grid_clb grid_clb_1__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_0_ccff_tail[0])); + grid_clb + grid_clb_2__1_ + ( + .SC_OUT_TOP(scff_Wires[9]), + .SC_IN_BOT(scff_Wires[8]), + .top_width_0_height_0__pin_33_(sc_in_wires[1]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), + .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(cby_1__1__0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_2_ccff_tail[0]) + ); - grid_clb grid_clb_1__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), - .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), - .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_1_ccff_tail[0])); - grid_clb grid_clb_2__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_2_ccff_tail[0])); + grid_clb + grid_clb_2__2_ + ( + .SC_OUT_TOP(scff_Wires[11]), + .SC_IN_BOT(scff_Wires[10]), + .bottom_width_0_height_0__pin_51_(sc_out_wires[1]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), + .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(cby_1__1__1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .ccff_tail(grid_clb_3_ccff_tail[0]) + ); - grid_clb grid_clb_2__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_3_ccff_tail[0])); - grid_io_top grid_io_top_1__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__0_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_0_ccff_tail[0])); + sb_0__0_ + sb_0__0_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), + .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .chany_top_out(sb_0__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), + .ccff_tail(ccff_tail[0]) + ); - grid_io_top grid_io_top_2__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__1_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_1_ccff_tail[0])); - grid_io_right grid_io_right_3__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), - .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__2_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_0_ccff_tail[0])); + sb_0__1_ + sb_0__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), + .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(cbx_1__1__0_ccff_tail[0]), + .chany_top_out(sb_0__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__1__0_ccff_tail[0]) + ); - grid_io_right grid_io_right_3__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), - .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__3_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_1_ccff_tail[0])); - grid_io_bottom grid_io_bottom_1__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), - .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .ccff_head(cbx_1__0__0_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + sb_0__2_ + sb_0__2_ + ( + .SC_OUT_BOT(scff_Wires[0]), + .SC_IN_TOP(sc_head), + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_0_ccff_tail[0]), + .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__2__0_ccff_tail[0]) + ); - grid_io_bottom grid_io_bottom_2__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), - .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .ccff_head(cbx_1__0__1_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_1_ccff_tail[0])); - grid_io_left grid_io_left_0__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), - .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_0_ccff_tail[0])); + sb_1__0_ + sb_1__0_ + ( + .SC_OUT_BOT(scff_Wires[7]), + .SC_IN_TOP(scff_Wires[6]), + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), + .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), + .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), + .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .chany_top_out(sb_1__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__0__0_ccff_tail[0]) + ); - grid_io_left grid_io_left_0__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), - .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_1_ccff_tail[0])); - sb_0__0_ sb_0__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_bottom_0_ccff_tail[0]), - .chany_top_out(sb_0__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), - .ccff_tail(ccff_tail[0])); + sb_1__1_ + sb_1__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), + .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), + .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), + .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(cbx_1__1__1_ccff_tail[0]), + .chany_top_out(sb_1__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__1__0_ccff_tail[0]) + ); - sb_0__1_ sb_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(cbx_1__1__0_ccff_tail[0]), - .chany_top_out(sb_0__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__1__0_ccff_tail[0])); - sb_0__2_ sb_0__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_0_ccff_tail[0]), - .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__2__0_ccff_tail[0])); + sb_1__2_ + sb_1__2_ + ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_top_1_ccff_tail[0]), + .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__2__0_ccff_tail[0]) + ); - sb_1__0_ sb_1__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_bottom_1_ccff_tail[0]), - .chany_top_out(sb_1__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), - .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__0__0_ccff_tail[0])); - sb_1__1_ sb_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(cbx_1__1__1_ccff_tail[0]), - .chany_top_out(sb_1__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__1__0_ccff_tail[0])); + sb_2__0_ + sb_2__0_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), + .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_right_0_ccff_tail[0]), + .chany_top_out(sb_2__0__0_chany_top_out[0:19]), + .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__0__0_ccff_tail[0]) + ); - sb_1__2_ sb_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_top_1_ccff_tail[0]), - .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__2__0_ccff_tail[0])); - sb_2__0_ sb_2__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_right_0_ccff_tail[0]), - .chany_top_out(sb_2__0__0_chany_top_out[0:19]), - .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__0__0_ccff_tail[0])); + sb_2__1_ + sb_2__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), + .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_right_1_ccff_tail[0]), + .chany_top_out(sb_2__1__0_chany_top_out[0:19]), + .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__1__0_ccff_tail[0]) + ); - sb_2__1_ sb_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(grid_io_right_1_ccff_tail[0]), - .chany_top_out(sb_2__1__0_chany_top_out[0:19]), - .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__1__0_ccff_tail[0])); - sb_2__2_ sb_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(ccff_head[0]), - .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__2__0_ccff_tail[0])); + sb_2__2_ + sb_2__2_ + ( + .SC_OUT_TOP(sc_tail), + .SC_IN_TOP(scff_Wires[12]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(ccff_head[0]), + .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__2__0_ccff_tail[0]) + ); - cbx_1__0_ cbx_1__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), - .ccff_head(sb_1__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .ccff_tail(cbx_1__0__0_ccff_tail[0])); - cbx_1__0_ cbx_2__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), - .ccff_head(sb_2__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .ccff_tail(cbx_1__0__1_ccff_tail[0])); + cbx_1__0_ + cbx_1__0_ + ( + .SC_OUT_BOT(scff_Wires[6]), + .SC_IN_TOP(scff_Wires[5]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), + .ccff_head(sb_1__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), + .ccff_tail(grid_io_bottom_0_ccff_tail[0]) + ); - cbx_1__1_ cbx_1__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), - .ccff_head(sb_1__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .ccff_tail(cbx_1__1__0_ccff_tail[0])); - cbx_1__1_ cbx_2__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), - .ccff_head(sb_2__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .ccff_tail(cbx_1__1__1_ccff_tail[0])); + cbx_1__0_ + cbx_2__0_ + ( + .SC_OUT_TOP(scff_Wires[8]), + .SC_IN_TOP(scff_Wires[7]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), + .ccff_head(sb_2__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), + .ccff_tail(grid_io_bottom_1_ccff_tail[0]) + ); - cbx_1__2_ cbx_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), - .ccff_head(sb_1__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .ccff_tail(cbx_1__2__0_ccff_tail[0])); - cbx_1__2_ cbx_2__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), - .ccff_head(sb_2__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .ccff_tail(cbx_1__2__1_ccff_tail[0])); + cbx_1__1_ + cbx_1__1_ + ( + .SC_OUT_BOT(scff_Wires[3]), + .SC_IN_TOP(scff_Wires[2]), + .CLB_SC_OUT(sc_in_wires[0]), + .CLB_SC_IN(sc_out_wires[0]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), + .ccff_head(sb_1__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), + .ccff_tail(cbx_1__1__0_ccff_tail[0]) + ); - cby_0__1_ cby_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), - .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__1__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__0_ccff_tail[0])); - cby_0__1_ cby_0__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), - .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__2__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__1_ccff_tail[0])); + cbx_1__1_ + cbx_2__1_ + ( + .SC_OUT_TOP(scff_Wires[10]), + .SC_IN_BOT(scff_Wires[9]), + .CLB_SC_OUT(sc_in_wires[1]), + .CLB_SC_IN(sc_out_wires[1]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), + .ccff_head(sb_2__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), + .ccff_tail(cbx_1__1__1_ccff_tail[0]) + ); - cby_1__1_ cby_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), - .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_0_ccff_tail[0]), - .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__0_ccff_tail[0])); - cby_1__1_ cby_1__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), - .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_1_ccff_tail[0]), - .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__1_ccff_tail[0])); + cbx_1__2_ + cbx_1__2_ + ( + .SC_OUT_BOT(scff_Wires[1]), + .SC_IN_TOP(scff_Wires[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), + .ccff_head(sb_1__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), + .ccff_tail(grid_io_top_0_ccff_tail[0]) + ); - cby_1__1_ cby_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), - .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__2_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__2_ccff_tail[0])); - cby_1__1_ cby_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), - .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__3_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__3_ccff_tail[0])); + cbx_1__2_ + cbx_2__2_ + ( + .SC_OUT_BOT(scff_Wires[12]), + .SC_IN_BOT(scff_Wires[11]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), + .ccff_head(sb_2__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), + .ccff_tail(grid_io_top_1_ccff_tail[0]) + ); - direct_interc direct_interc_0_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_0_out[0])); - direct_interc direct_interc_1_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_1_out[0])); + cby_0__1_ + cby_0__1_ + ( + .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__1__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__0_chany_top_out[0:19]), + .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_tail(grid_io_left_0_ccff_tail[0]) + ); - direct_interc direct_interc_2_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_2_out[0])); - direct_interc direct_interc_3_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_3_out[0])); + cby_0__1_ + cby_0__2_ + ( + .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), + .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__2__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__1_chany_top_out[0:19]), + .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_tail(grid_io_left_1_ccff_tail[0]) + ); - direct_interc direct_interc_4_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_4_out[0])); - direct_interc direct_interc_5_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_5_out[0])); + cby_1__1_ + cby_1__1_ + ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_0_ccff_tail[0]), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__0_chany_top_out[0:19]), + .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .ccff_tail(cby_1__1__0_ccff_tail[0]) + ); + + + cby_1__1_ + cby_1__2_ + ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), + .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_1_ccff_tail[0]), + .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__1_chany_top_out[0:19]), + .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .ccff_tail(cby_1__1__1_ccff_tail[0]) + ); + + + cby_2__1_ + cby_2__1_ + ( + .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), + .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_2_ccff_tail[0]), + .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__0_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .ccff_tail(grid_io_right_0_ccff_tail[0]) + ); + + + cby_2__1_ + cby_2__2_ + ( + .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), + .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_3_ccff_tail[0]), + .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__1_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .ccff_tail(grid_io_right_1_ccff_tail[0]) + ); + + + direct_interc + direct_interc_0_ + ( + .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_0_out[0]) + ); + + + direct_interc + direct_interc_1_ + ( + .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_1_out[0]) + ); + + + direct_interc + direct_interc_2_ + ( + .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_2_out[0]) + ); + + + direct_interc + direct_interc_3_ + ( + .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_3_out[0]) + ); + + + direct_interc + direct_interc_4_ + ( + .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_4_out[0]) + ); + + + direct_interc + direct_interc_5_ + ( + .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_5_out[0]) + ); + endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v index 5ccd1a3..b283491 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v @@ -9,14 +9,14 @@ `timescale 1ns / 1ps // -module fpga_topfpga_top(prog_clk, Test_en, clk, gfpga_pad_GPIO_A, gfpga_pad_GPIO_IE, gfpga_pad_GPIO_OE, gfpga_pad_GPIO_Y, ccff_head, ccff_tail); prog_clk; - Test_en; - clk; - gfpga_pad_GPIO_A; - gfpga_pad_GPIO_IE; - gfpga_pad_GPIO_OE; - gfpga_pad_GPIO_Y; - ccff_head;; +module fpga_top(prog_clk, + Test_en, + clk, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + ccff_head, + ccff_tail); // input [0:0] prog_clk; // @@ -24,13 +24,11 @@ input [0:0] Test_en; // input [0:0] clk; // -output [0:7] gfpga_pad_GPIO_A; +input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:7] gfpga_pad_GPIO_IE; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:7] gfpga_pad_GPIO_OE; -// -inout [0:7] gfpga_pad_GPIO_Y; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] ccff_head; // @@ -45,87 +43,97 @@ output [0:0] ccff_tail; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; wire [0:0] cbx_1__0__0_ccff_tail; wire [0:19] cbx_1__0__0_chanx_left_out; wire [0:19] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__0__0_top_grid_pin_16_; -wire [0:0] cbx_1__0__0_top_grid_pin_17_; -wire [0:0] cbx_1__0__0_top_grid_pin_18_; -wire [0:0] cbx_1__0__0_top_grid_pin_19_; -wire [0:0] cbx_1__0__0_top_grid_pin_20_; -wire [0:0] cbx_1__0__0_top_grid_pin_21_; -wire [0:0] cbx_1__0__0_top_grid_pin_22_; -wire [0:0] cbx_1__0__0_top_grid_pin_23_; -wire [0:0] cbx_1__0__0_top_grid_pin_24_; -wire [0:0] cbx_1__0__0_top_grid_pin_25_; -wire [0:0] cbx_1__0__0_top_grid_pin_26_; -wire [0:0] cbx_1__0__0_top_grid_pin_27_; -wire [0:0] cbx_1__0__0_top_grid_pin_28_; -wire [0:0] cbx_1__0__0_top_grid_pin_29_; -wire [0:0] cbx_1__0__0_top_grid_pin_30_; -wire [0:0] cbx_1__0__0_top_grid_pin_31_; wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; wire [0:0] cbx_1__0__1_ccff_tail; wire [0:19] cbx_1__0__1_chanx_left_out; wire [0:19] cbx_1__0__1_chanx_right_out; -wire [0:0] cbx_1__0__1_top_grid_pin_16_; -wire [0:0] cbx_1__0__1_top_grid_pin_17_; -wire [0:0] cbx_1__0__1_top_grid_pin_18_; -wire [0:0] cbx_1__0__1_top_grid_pin_19_; -wire [0:0] cbx_1__0__1_top_grid_pin_20_; -wire [0:0] cbx_1__0__1_top_grid_pin_21_; -wire [0:0] cbx_1__0__1_top_grid_pin_22_; -wire [0:0] cbx_1__0__1_top_grid_pin_23_; -wire [0:0] cbx_1__0__1_top_grid_pin_24_; -wire [0:0] cbx_1__0__1_top_grid_pin_25_; -wire [0:0] cbx_1__0__1_top_grid_pin_26_; -wire [0:0] cbx_1__0__1_top_grid_pin_27_; -wire [0:0] cbx_1__0__1_top_grid_pin_28_; -wire [0:0] cbx_1__0__1_top_grid_pin_29_; -wire [0:0] cbx_1__0__1_top_grid_pin_30_; -wire [0:0] cbx_1__0__1_top_grid_pin_31_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; wire [0:0] cbx_1__1__0_ccff_tail; wire [0:19] cbx_1__1__0_chanx_left_out; wire [0:19] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__0_top_grid_pin_16_; -wire [0:0] cbx_1__1__0_top_grid_pin_17_; -wire [0:0] cbx_1__1__0_top_grid_pin_18_; -wire [0:0] cbx_1__1__0_top_grid_pin_19_; -wire [0:0] cbx_1__1__0_top_grid_pin_20_; -wire [0:0] cbx_1__1__0_top_grid_pin_21_; -wire [0:0] cbx_1__1__0_top_grid_pin_22_; -wire [0:0] cbx_1__1__0_top_grid_pin_23_; -wire [0:0] cbx_1__1__0_top_grid_pin_24_; -wire [0:0] cbx_1__1__0_top_grid_pin_25_; -wire [0:0] cbx_1__1__0_top_grid_pin_26_; -wire [0:0] cbx_1__1__0_top_grid_pin_27_; -wire [0:0] cbx_1__1__0_top_grid_pin_28_; -wire [0:0] cbx_1__1__0_top_grid_pin_29_; -wire [0:0] cbx_1__1__0_top_grid_pin_30_; -wire [0:0] cbx_1__1__0_top_grid_pin_31_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; wire [0:0] cbx_1__1__1_ccff_tail; wire [0:19] cbx_1__1__1_chanx_left_out; wire [0:19] cbx_1__1__1_chanx_right_out; -wire [0:0] cbx_1__1__1_top_grid_pin_16_; -wire [0:0] cbx_1__1__1_top_grid_pin_17_; -wire [0:0] cbx_1__1__1_top_grid_pin_18_; -wire [0:0] cbx_1__1__1_top_grid_pin_19_; -wire [0:0] cbx_1__1__1_top_grid_pin_20_; -wire [0:0] cbx_1__1__1_top_grid_pin_21_; -wire [0:0] cbx_1__1__1_top_grid_pin_22_; -wire [0:0] cbx_1__1__1_top_grid_pin_23_; -wire [0:0] cbx_1__1__1_top_grid_pin_24_; -wire [0:0] cbx_1__1__1_top_grid_pin_25_; -wire [0:0] cbx_1__1__1_top_grid_pin_26_; -wire [0:0] cbx_1__1__1_top_grid_pin_27_; -wire [0:0] cbx_1__1__1_top_grid_pin_28_; -wire [0:0] cbx_1__1__1_top_grid_pin_29_; -wire [0:0] cbx_1__1__1_top_grid_pin_30_; -wire [0:0] cbx_1__1__1_top_grid_pin_31_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; wire [0:0] cbx_1__2__0_ccff_tail; wire [0:19] cbx_1__2__0_chanx_left_out; wire [0:19] cbx_1__2__0_chanx_right_out; wire [0:0] cbx_1__2__0_top_grid_pin_0_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; wire [0:0] cbx_1__2__1_ccff_tail; wire [0:19] cbx_1__2__1_chanx_left_out; wire [0:19] cbx_1__2__1_chanx_right_out; @@ -134,264 +142,284 @@ wire [0:0] cby_0__1__0_ccff_tail; wire [0:19] cby_0__1__0_chany_bottom_out; wire [0:19] cby_0__1__0_chany_top_out; wire [0:0] cby_0__1__0_left_grid_pin_0_; -wire [0:0] cby_0__1__0_right_grid_pin_52_; wire [0:0] cby_0__1__1_ccff_tail; wire [0:19] cby_0__1__1_chany_bottom_out; wire [0:19] cby_0__1__1_chany_top_out; wire [0:0] cby_0__1__1_left_grid_pin_0_; -wire [0:0] cby_0__1__1_right_grid_pin_52_; wire [0:0] cby_1__1__0_ccff_tail; wire [0:19] cby_1__1__0_chany_bottom_out; wire [0:19] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_pin_0_; -wire [0:0] cby_1__1__0_left_grid_pin_10_; -wire [0:0] cby_1__1__0_left_grid_pin_11_; -wire [0:0] cby_1__1__0_left_grid_pin_12_; -wire [0:0] cby_1__1__0_left_grid_pin_13_; -wire [0:0] cby_1__1__0_left_grid_pin_14_; -wire [0:0] cby_1__1__0_left_grid_pin_15_; -wire [0:0] cby_1__1__0_left_grid_pin_1_; -wire [0:0] cby_1__1__0_left_grid_pin_2_; -wire [0:0] cby_1__1__0_left_grid_pin_3_; -wire [0:0] cby_1__1__0_left_grid_pin_4_; -wire [0:0] cby_1__1__0_left_grid_pin_5_; -wire [0:0] cby_1__1__0_left_grid_pin_6_; -wire [0:0] cby_1__1__0_left_grid_pin_7_; -wire [0:0] cby_1__1__0_left_grid_pin_8_; -wire [0:0] cby_1__1__0_left_grid_pin_9_; -wire [0:0] cby_1__1__0_right_grid_pin_52_; +wire [0:0] cby_1__1__0_left_grid_pin_16_; +wire [0:0] cby_1__1__0_left_grid_pin_17_; +wire [0:0] cby_1__1__0_left_grid_pin_18_; +wire [0:0] cby_1__1__0_left_grid_pin_19_; +wire [0:0] cby_1__1__0_left_grid_pin_20_; +wire [0:0] cby_1__1__0_left_grid_pin_21_; +wire [0:0] cby_1__1__0_left_grid_pin_22_; +wire [0:0] cby_1__1__0_left_grid_pin_23_; +wire [0:0] cby_1__1__0_left_grid_pin_24_; +wire [0:0] cby_1__1__0_left_grid_pin_25_; +wire [0:0] cby_1__1__0_left_grid_pin_26_; +wire [0:0] cby_1__1__0_left_grid_pin_27_; +wire [0:0] cby_1__1__0_left_grid_pin_28_; +wire [0:0] cby_1__1__0_left_grid_pin_29_; +wire [0:0] cby_1__1__0_left_grid_pin_30_; +wire [0:0] cby_1__1__0_left_grid_pin_31_; wire [0:0] cby_1__1__1_ccff_tail; wire [0:19] cby_1__1__1_chany_bottom_out; wire [0:19] cby_1__1__1_chany_top_out; -wire [0:0] cby_1__1__1_left_grid_pin_0_; -wire [0:0] cby_1__1__1_left_grid_pin_10_; -wire [0:0] cby_1__1__1_left_grid_pin_11_; -wire [0:0] cby_1__1__1_left_grid_pin_12_; -wire [0:0] cby_1__1__1_left_grid_pin_13_; -wire [0:0] cby_1__1__1_left_grid_pin_14_; -wire [0:0] cby_1__1__1_left_grid_pin_15_; -wire [0:0] cby_1__1__1_left_grid_pin_1_; -wire [0:0] cby_1__1__1_left_grid_pin_2_; -wire [0:0] cby_1__1__1_left_grid_pin_3_; -wire [0:0] cby_1__1__1_left_grid_pin_4_; -wire [0:0] cby_1__1__1_left_grid_pin_5_; -wire [0:0] cby_1__1__1_left_grid_pin_6_; -wire [0:0] cby_1__1__1_left_grid_pin_7_; -wire [0:0] cby_1__1__1_left_grid_pin_8_; -wire [0:0] cby_1__1__1_left_grid_pin_9_; -wire [0:0] cby_1__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__2_ccff_tail; -wire [0:19] cby_1__1__2_chany_bottom_out; -wire [0:19] cby_1__1__2_chany_top_out; -wire [0:0] cby_1__1__2_left_grid_pin_0_; -wire [0:0] cby_1__1__2_left_grid_pin_10_; -wire [0:0] cby_1__1__2_left_grid_pin_11_; -wire [0:0] cby_1__1__2_left_grid_pin_12_; -wire [0:0] cby_1__1__2_left_grid_pin_13_; -wire [0:0] cby_1__1__2_left_grid_pin_14_; -wire [0:0] cby_1__1__2_left_grid_pin_15_; -wire [0:0] cby_1__1__2_left_grid_pin_1_; -wire [0:0] cby_1__1__2_left_grid_pin_2_; -wire [0:0] cby_1__1__2_left_grid_pin_3_; -wire [0:0] cby_1__1__2_left_grid_pin_4_; -wire [0:0] cby_1__1__2_left_grid_pin_5_; -wire [0:0] cby_1__1__2_left_grid_pin_6_; -wire [0:0] cby_1__1__2_left_grid_pin_7_; -wire [0:0] cby_1__1__2_left_grid_pin_8_; -wire [0:0] cby_1__1__2_left_grid_pin_9_; -wire [0:0] cby_1__1__2_right_grid_pin_52_; -wire [0:0] cby_1__1__3_ccff_tail; -wire [0:19] cby_1__1__3_chany_bottom_out; -wire [0:19] cby_1__1__3_chany_top_out; -wire [0:0] cby_1__1__3_left_grid_pin_0_; -wire [0:0] cby_1__1__3_left_grid_pin_10_; -wire [0:0] cby_1__1__3_left_grid_pin_11_; -wire [0:0] cby_1__1__3_left_grid_pin_12_; -wire [0:0] cby_1__1__3_left_grid_pin_13_; -wire [0:0] cby_1__1__3_left_grid_pin_14_; -wire [0:0] cby_1__1__3_left_grid_pin_15_; -wire [0:0] cby_1__1__3_left_grid_pin_1_; -wire [0:0] cby_1__1__3_left_grid_pin_2_; -wire [0:0] cby_1__1__3_left_grid_pin_3_; -wire [0:0] cby_1__1__3_left_grid_pin_4_; -wire [0:0] cby_1__1__3_left_grid_pin_5_; -wire [0:0] cby_1__1__3_left_grid_pin_6_; -wire [0:0] cby_1__1__3_left_grid_pin_7_; -wire [0:0] cby_1__1__3_left_grid_pin_8_; -wire [0:0] cby_1__1__3_left_grid_pin_9_; -wire [0:0] cby_1__1__3_right_grid_pin_52_; +wire [0:0] cby_1__1__1_left_grid_pin_16_; +wire [0:0] cby_1__1__1_left_grid_pin_17_; +wire [0:0] cby_1__1__1_left_grid_pin_18_; +wire [0:0] cby_1__1__1_left_grid_pin_19_; +wire [0:0] cby_1__1__1_left_grid_pin_20_; +wire [0:0] cby_1__1__1_left_grid_pin_21_; +wire [0:0] cby_1__1__1_left_grid_pin_22_; +wire [0:0] cby_1__1__1_left_grid_pin_23_; +wire [0:0] cby_1__1__1_left_grid_pin_24_; +wire [0:0] cby_1__1__1_left_grid_pin_25_; +wire [0:0] cby_1__1__1_left_grid_pin_26_; +wire [0:0] cby_1__1__1_left_grid_pin_27_; +wire [0:0] cby_1__1__1_left_grid_pin_28_; +wire [0:0] cby_1__1__1_left_grid_pin_29_; +wire [0:0] cby_1__1__1_left_grid_pin_30_; +wire [0:0] cby_1__1__1_left_grid_pin_31_; +wire [0:0] cby_2__1__0_ccff_tail; +wire [0:19] cby_2__1__0_chany_bottom_out; +wire [0:19] cby_2__1__0_chany_top_out; +wire [0:0] cby_2__1__0_left_grid_pin_16_; +wire [0:0] cby_2__1__0_left_grid_pin_17_; +wire [0:0] cby_2__1__0_left_grid_pin_18_; +wire [0:0] cby_2__1__0_left_grid_pin_19_; +wire [0:0] cby_2__1__0_left_grid_pin_20_; +wire [0:0] cby_2__1__0_left_grid_pin_21_; +wire [0:0] cby_2__1__0_left_grid_pin_22_; +wire [0:0] cby_2__1__0_left_grid_pin_23_; +wire [0:0] cby_2__1__0_left_grid_pin_24_; +wire [0:0] cby_2__1__0_left_grid_pin_25_; +wire [0:0] cby_2__1__0_left_grid_pin_26_; +wire [0:0] cby_2__1__0_left_grid_pin_27_; +wire [0:0] cby_2__1__0_left_grid_pin_28_; +wire [0:0] cby_2__1__0_left_grid_pin_29_; +wire [0:0] cby_2__1__0_left_grid_pin_30_; +wire [0:0] cby_2__1__0_left_grid_pin_31_; +wire [0:0] cby_2__1__0_right_grid_pin_0_; +wire [0:0] cby_2__1__1_ccff_tail; +wire [0:19] cby_2__1__1_chany_bottom_out; +wire [0:19] cby_2__1__1_chany_top_out; +wire [0:0] cby_2__1__1_left_grid_pin_16_; +wire [0:0] cby_2__1__1_left_grid_pin_17_; +wire [0:0] cby_2__1__1_left_grid_pin_18_; +wire [0:0] cby_2__1__1_left_grid_pin_19_; +wire [0:0] cby_2__1__1_left_grid_pin_20_; +wire [0:0] cby_2__1__1_left_grid_pin_21_; +wire [0:0] cby_2__1__1_left_grid_pin_22_; +wire [0:0] cby_2__1__1_left_grid_pin_23_; +wire [0:0] cby_2__1__1_left_grid_pin_24_; +wire [0:0] cby_2__1__1_left_grid_pin_25_; +wire [0:0] cby_2__1__1_left_grid_pin_26_; +wire [0:0] cby_2__1__1_left_grid_pin_27_; +wire [0:0] cby_2__1__1_left_grid_pin_28_; +wire [0:0] cby_2__1__1_left_grid_pin_29_; +wire [0:0] cby_2__1__1_left_grid_pin_30_; +wire [0:0] cby_2__1__1_left_grid_pin_31_; +wire [0:0] cby_2__1__1_right_grid_pin_0_; wire [0:0] direct_interc_0_out; wire [0:0] direct_interc_1_out; wire [0:0] direct_interc_2_out; wire [0:0] direct_interc_3_out; wire [0:0] direct_interc_4_out; wire [0:0] direct_interc_5_out; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_0_ccff_tail; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; +wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_1_ccff_tail; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; +wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; wire [0:0] grid_clb_2_ccff_tail; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_3_ccff_tail; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_io_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_1_ccff_tail; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_0_ccff_tail; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_1_ccff_tail; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_0_ccff_tail; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_1_ccff_tail; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_ccff_tail; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_1_ccff_tail; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; +wire [0:0] grid_io_bottom_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper; +wire [0:0] grid_io_bottom_bottom_1_ccff_tail; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper; +wire [0:0] grid_io_left_left_0_ccff_tail; +wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_left_1_ccff_tail; +wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_right_0_ccff_tail; +wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_right_1_ccff_tail; +wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_0_ccff_tail; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_1_ccff_tail; wire [0:19] sb_0__0__0_chanx_right_out; wire [0:19] sb_0__0__0_chany_top_out; wire [0:0] sb_0__1__0_ccff_tail; @@ -434,74 +462,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_left_0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_0_ccff_tail[0])); @@ -510,74 +538,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), - .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_left_1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_1_ccff_tail[0])); @@ -586,74 +614,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), .ccff_head(cby_1__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_2_ccff_tail[0])); @@ -662,189 +690,208 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), .ccff_head(cby_1__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_3_ccff_tail[0])); - grid_io_top grid_io_top_1__3_ ( + grid_io_top_top grid_io_top_top_1__3_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), .ccff_head(cbx_1__2__0_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_0_ccff_tail[0])); + .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_top_0_ccff_tail[0])); - grid_io_top grid_io_top_2__3_ ( + grid_io_top_top grid_io_top_top_2__3_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), .ccff_head(cbx_1__2__1_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_1_ccff_tail[0])); + .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_top_1_ccff_tail[0])); - grid_io_right grid_io_right_3__1_ ( + grid_io_right_right grid_io_right_right_3__1_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), - .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__2_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_0_ccff_tail[0])); + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .ccff_head(cby_2__1__0_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_right_0_ccff_tail[0])); - grid_io_right grid_io_right_3__2_ ( + grid_io_right_right grid_io_right_right_3__2_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), - .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__3_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_1_ccff_tail[0])); + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .ccff_head(cby_2__1__1_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_right_1_ccff_tail[0])); - grid_io_bottom grid_io_bottom_1__0_ ( + grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), .ccff_head(cbx_1__0__0_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail[0])); - grid_io_bottom grid_io_bottom_2__0_ ( + grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), .ccff_head(cbx_1__0__1_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_1_ccff_tail[0])); + .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail[0])); - grid_io_left grid_io_left_0__1_ ( + grid_io_left_left grid_io_left_left_0__1_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), .ccff_head(cby_0__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_0_ccff_tail[0])); + .right_width_0_height_0__pin_1_upper(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_left_0_ccff_tail[0])); - grid_io_left grid_io_left_0__2_ ( + grid_io_left_left grid_io_left_left_0__2_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), .ccff_head(cby_0__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_1_ccff_tail[0])); + .right_width_0_height_0__pin_1_upper(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_left_1_ccff_tail[0])); sb_0__0_ sb_0__0_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .top_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .ccff_head(grid_io_bottom_bottom_0_ccff_tail[0]), .chany_top_out(sb_0__0__0_chany_top_out[0:19]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), .ccff_tail(ccff_tail[0])); @@ -852,18 +899,18 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_0__1_ sb_0__1_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .top_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), .ccff_head(cbx_1__1__0_ccff_tail[0]), .chany_top_out(sb_0__1__0_chany_top_out[0:19]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), @@ -873,10 +920,18 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_0__2_ sb_0__2_ ( .prog_clk(prog_clk[0]), .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_0_ccff_tail[0]), + .bottom_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_top_0_ccff_tail[0]), .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), .ccff_tail(sb_0__2__0_ccff_tail[0])); @@ -884,35 +939,29 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__0_ sb_1__0_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail[0]), .chany_top_out(sb_1__0__0_chany_top_out[0:19]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), @@ -921,41 +970,41 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__1_ sb_1__1_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), .ccff_head(cbx_1__1__1_ccff_tail[0]), .chany_top_out(sb_1__1__0_chany_top_out[0:19]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), @@ -966,19 +1015,35 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__2_ sb_1__2_ ( .prog_clk(prog_clk[0]), .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_top_1_ccff_tail[0]), + .left_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_top_top_1_ccff_tail[0]), .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), @@ -986,63 +1051,60 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_2__0_ sb_2__0_ ( .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_right_0_ccff_tail[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_right_right_0_ccff_tail[0]), .chany_top_out(sb_2__0__0_chany_top_out[0:19]), .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), .ccff_tail(sb_2__0__0_ccff_tail[0])); sb_2__1_ sb_2__1_ ( .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(grid_io_right_1_ccff_tail[0]), + .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_right_right_1_ccff_tail[0]), .chany_top_out(sb_2__1__0_chany_top_out[0:19]), .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), @@ -1050,18 +1112,26 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_2__2_ sb_2__2_ ( .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), .ccff_head(ccff_head[0]), .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), @@ -1074,23 +1144,12 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_1__0__0_ccff_tail[0]), .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), .ccff_tail(cbx_1__0__0_ccff_tail[0])); cbx_1__0_ cbx_2__0_ ( @@ -1100,23 +1159,12 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_2__0__0_ccff_tail[0]), .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), .ccff_tail(cbx_1__0__1_ccff_tail[0])); cbx_1__1_ cbx_1__1_ ( @@ -1126,22 +1174,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_1__1__0_ccff_tail[0]), .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__1__0_ccff_tail[0])); cbx_1__1_ cbx_2__1_ ( @@ -1151,22 +1199,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_2__1__0_ccff_tail[0]), .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__1__1_ccff_tail[0])); cbx_1__2_ cbx_1__2_ ( @@ -1177,6 +1225,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__2__0_ccff_tail[0])); cbx_1__2_ cbx_2__2_ ( @@ -1187,6 +1251,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__2__1_ccff_tail[0])); cby_0__1_ cby_0__1_ ( @@ -1196,7 +1276,6 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_0__1__0_ccff_tail[0]), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), .ccff_tail(cby_0__1__0_ccff_tail[0])); @@ -1207,7 +1286,6 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_0__2__0_ccff_tail[0]), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), .ccff_tail(cby_0__1__1_ccff_tail[0])); @@ -1218,23 +1296,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(grid_clb_0_ccff_tail[0]), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), .ccff_tail(cby_1__1__0_ccff_tail[0])); cby_1__1_ cby_1__2_ ( @@ -1244,76 +1321,75 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(grid_clb_1_ccff_tail[0]), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), .ccff_tail(cby_1__1__1_ccff_tail[0])); - cby_1__1_ cby_2__1_ ( + cby_2__1_ cby_2__1_ ( .prog_clk(prog_clk[0]), .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__2_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__2_ccff_tail[0])); + .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__0_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .ccff_tail(cby_2__1__0_ccff_tail[0])); - cby_1__1_ cby_2__2_ ( + cby_2__1_ cby_2__2_ ( .prog_clk(prog_clk[0]), .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__3_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__3_ccff_tail[0])); + .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__1_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .ccff_tail(cby_2__1__1_ccff_tail[0])); direct_interc direct_interc_0_ ( .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v index e0f7d9d..03671f6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v @@ -1,292 +1,138 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_clb(prog_clk, - Test_en, - clk, - top_width_0_height_0__pin_32_, - top_width_0_height_0__pin_33_, - right_width_0_height_0__pin_0_, - right_width_0_height_0__pin_1_, - right_width_0_height_0__pin_2_, - right_width_0_height_0__pin_3_, - right_width_0_height_0__pin_4_, - right_width_0_height_0__pin_5_, - right_width_0_height_0__pin_6_, - right_width_0_height_0__pin_7_, - right_width_0_height_0__pin_8_, - right_width_0_height_0__pin_9_, - right_width_0_height_0__pin_10_, - right_width_0_height_0__pin_11_, - right_width_0_height_0__pin_12_, - right_width_0_height_0__pin_13_, - right_width_0_height_0__pin_14_, - right_width_0_height_0__pin_15_, - bottom_width_0_height_0__pin_16_, - bottom_width_0_height_0__pin_17_, - bottom_width_0_height_0__pin_18_, - bottom_width_0_height_0__pin_19_, - bottom_width_0_height_0__pin_20_, - bottom_width_0_height_0__pin_21_, - bottom_width_0_height_0__pin_22_, - bottom_width_0_height_0__pin_23_, - bottom_width_0_height_0__pin_24_, - bottom_width_0_height_0__pin_25_, - bottom_width_0_height_0__pin_26_, - bottom_width_0_height_0__pin_27_, - bottom_width_0_height_0__pin_28_, - bottom_width_0_height_0__pin_29_, - bottom_width_0_height_0__pin_30_, - bottom_width_0_height_0__pin_31_, - left_width_0_height_0__pin_52_, - ccff_head, - right_width_0_height_0__pin_34_upper, - right_width_0_height_0__pin_34_lower, - right_width_0_height_0__pin_35_upper, - right_width_0_height_0__pin_35_lower, - right_width_0_height_0__pin_36_upper, - right_width_0_height_0__pin_36_lower, - right_width_0_height_0__pin_37_upper, - right_width_0_height_0__pin_37_lower, - right_width_0_height_0__pin_38_upper, - right_width_0_height_0__pin_38_lower, - right_width_0_height_0__pin_39_upper, - right_width_0_height_0__pin_39_lower, - right_width_0_height_0__pin_40_upper, - right_width_0_height_0__pin_40_lower, - right_width_0_height_0__pin_41_upper, - right_width_0_height_0__pin_41_lower, - bottom_width_0_height_0__pin_42_upper, - bottom_width_0_height_0__pin_42_lower, - bottom_width_0_height_0__pin_43_upper, - bottom_width_0_height_0__pin_43_lower, - bottom_width_0_height_0__pin_44_upper, - bottom_width_0_height_0__pin_44_lower, - bottom_width_0_height_0__pin_45_upper, - bottom_width_0_height_0__pin_45_lower, - bottom_width_0_height_0__pin_46_upper, - bottom_width_0_height_0__pin_46_lower, - bottom_width_0_height_0__pin_47_upper, - bottom_width_0_height_0__pin_47_lower, - bottom_width_0_height_0__pin_48_upper, - bottom_width_0_height_0__pin_48_lower, - bottom_width_0_height_0__pin_49_upper, - bottom_width_0_height_0__pin_49_lower, - bottom_width_0_height_0__pin_50_, - bottom_width_0_height_0__pin_51_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:0] top_width_0_height_0__pin_32_; -// -input [0:0] top_width_0_height_0__pin_33_; -// -input [0:0] right_width_0_height_0__pin_0_; -// -input [0:0] right_width_0_height_0__pin_1_; -// -input [0:0] right_width_0_height_0__pin_2_; -// -input [0:0] right_width_0_height_0__pin_3_; -// -input [0:0] right_width_0_height_0__pin_4_; -// -input [0:0] right_width_0_height_0__pin_5_; -// -input [0:0] right_width_0_height_0__pin_6_; -// -input [0:0] right_width_0_height_0__pin_7_; -// -input [0:0] right_width_0_height_0__pin_8_; -// -input [0:0] right_width_0_height_0__pin_9_; -// -input [0:0] right_width_0_height_0__pin_10_; -// -input [0:0] right_width_0_height_0__pin_11_; -// -input [0:0] right_width_0_height_0__pin_12_; -// -input [0:0] right_width_0_height_0__pin_13_; -// -input [0:0] right_width_0_height_0__pin_14_; -// -input [0:0] right_width_0_height_0__pin_15_; -// -input [0:0] bottom_width_0_height_0__pin_16_; -// -input [0:0] bottom_width_0_height_0__pin_17_; -// -input [0:0] bottom_width_0_height_0__pin_18_; -// -input [0:0] bottom_width_0_height_0__pin_19_; -// -input [0:0] bottom_width_0_height_0__pin_20_; -// -input [0:0] bottom_width_0_height_0__pin_21_; -// -input [0:0] bottom_width_0_height_0__pin_22_; -// -input [0:0] bottom_width_0_height_0__pin_23_; -// -input [0:0] bottom_width_0_height_0__pin_24_; -// -input [0:0] bottom_width_0_height_0__pin_25_; -// -input [0:0] bottom_width_0_height_0__pin_26_; -// -input [0:0] bottom_width_0_height_0__pin_27_; -// -input [0:0] bottom_width_0_height_0__pin_28_; -// -input [0:0] bottom_width_0_height_0__pin_29_; -// -input [0:0] bottom_width_0_height_0__pin_30_; -// -input [0:0] bottom_width_0_height_0__pin_31_; -// -input [0:0] left_width_0_height_0__pin_52_; -// -input [0:0] ccff_head; -// -output [0:0] right_width_0_height_0__pin_34_upper; -// -output [0:0] right_width_0_height_0__pin_34_lower; -// -output [0:0] right_width_0_height_0__pin_35_upper; -// -output [0:0] right_width_0_height_0__pin_35_lower; -// -output [0:0] right_width_0_height_0__pin_36_upper; -// -output [0:0] right_width_0_height_0__pin_36_lower; -// -output [0:0] right_width_0_height_0__pin_37_upper; -// -output [0:0] right_width_0_height_0__pin_37_lower; -// -output [0:0] right_width_0_height_0__pin_38_upper; -// -output [0:0] right_width_0_height_0__pin_38_lower; -// -output [0:0] right_width_0_height_0__pin_39_upper; -// -output [0:0] right_width_0_height_0__pin_39_lower; -// -output [0:0] right_width_0_height_0__pin_40_upper; -// -output [0:0] right_width_0_height_0__pin_40_lower; -// -output [0:0] right_width_0_height_0__pin_41_upper; -// -output [0:0] right_width_0_height_0__pin_41_lower; -// -output [0:0] bottom_width_0_height_0__pin_42_upper; -// -output [0:0] bottom_width_0_height_0__pin_42_lower; -// -output [0:0] bottom_width_0_height_0__pin_43_upper; -// -output [0:0] bottom_width_0_height_0__pin_43_lower; -// -output [0:0] bottom_width_0_height_0__pin_44_upper; -// -output [0:0] bottom_width_0_height_0__pin_44_lower; -// -output [0:0] bottom_width_0_height_0__pin_45_upper; -// -output [0:0] bottom_width_0_height_0__pin_45_lower; -// -output [0:0] bottom_width_0_height_0__pin_46_upper; -// -output [0:0] bottom_width_0_height_0__pin_46_lower; -// -output [0:0] bottom_width_0_height_0__pin_47_upper; -// -output [0:0] bottom_width_0_height_0__pin_47_lower; -// -output [0:0] bottom_width_0_height_0__pin_48_upper; -// -output [0:0] bottom_width_0_height_0__pin_48_lower; -// -output [0:0] bottom_width_0_height_0__pin_49_upper; -// -output [0:0] bottom_width_0_height_0__pin_49_lower; -// -output [0:0] bottom_width_0_height_0__pin_50_; -// -output [0:0] bottom_width_0_height_0__pin_51_; -// -output [0:0] ccff_tail; - -// -// -// -// +module grid_clb +( + input [0:0] prog_clk, + input [0:0] Test_en, + input [0:0] clk, + input [0:0] top_width_0_height_0__pin_0_, + input [0:0] top_width_0_height_0__pin_1_, + input [0:0] top_width_0_height_0__pin_2_, + input [0:0] top_width_0_height_0__pin_3_, + input [0:0] top_width_0_height_0__pin_4_, + input [0:0] top_width_0_height_0__pin_5_, + input [0:0] top_width_0_height_0__pin_6_, + input [0:0] top_width_0_height_0__pin_7_, + input [0:0] top_width_0_height_0__pin_8_, + input [0:0] top_width_0_height_0__pin_9_, + input [0:0] top_width_0_height_0__pin_10_, + input [0:0] top_width_0_height_0__pin_11_, + input [0:0] top_width_0_height_0__pin_12_, + input [0:0] top_width_0_height_0__pin_13_, + input [0:0] top_width_0_height_0__pin_14_, + input [0:0] top_width_0_height_0__pin_15_, + input [0:0] top_width_0_height_0__pin_32_, + input [0:0] top_width_0_height_0__pin_33_, + input [0:0] right_width_0_height_0__pin_16_, + input [0:0] right_width_0_height_0__pin_17_, + input [0:0] right_width_0_height_0__pin_18_, + input [0:0] right_width_0_height_0__pin_19_, + input [0:0] right_width_0_height_0__pin_20_, + input [0:0] right_width_0_height_0__pin_21_, + input [0:0] right_width_0_height_0__pin_22_, + input [0:0] right_width_0_height_0__pin_23_, + input [0:0] right_width_0_height_0__pin_24_, + input [0:0] right_width_0_height_0__pin_25_, + input [0:0] right_width_0_height_0__pin_26_, + input [0:0] right_width_0_height_0__pin_27_, + input [0:0] right_width_0_height_0__pin_28_, + input [0:0] right_width_0_height_0__pin_29_, + input [0:0] right_width_0_height_0__pin_30_, + input [0:0] right_width_0_height_0__pin_31_, + input [0:0] left_width_0_height_0__pin_52_, + input [0:0] ccff_head, + output [0:0] top_width_0_height_0__pin_34_upper, + output [0:0] top_width_0_height_0__pin_34_lower, + output [0:0] top_width_0_height_0__pin_35_upper, + output [0:0] top_width_0_height_0__pin_35_lower, + output [0:0] top_width_0_height_0__pin_36_upper, + output [0:0] top_width_0_height_0__pin_36_lower, + output [0:0] top_width_0_height_0__pin_37_upper, + output [0:0] top_width_0_height_0__pin_37_lower, + output [0:0] top_width_0_height_0__pin_38_upper, + output [0:0] top_width_0_height_0__pin_38_lower, + output [0:0] top_width_0_height_0__pin_39_upper, + output [0:0] top_width_0_height_0__pin_39_lower, + output [0:0] top_width_0_height_0__pin_40_upper, + output [0:0] top_width_0_height_0__pin_40_lower, + output [0:0] top_width_0_height_0__pin_41_upper, + output [0:0] top_width_0_height_0__pin_41_lower, + output [0:0] right_width_0_height_0__pin_42_upper, + output [0:0] right_width_0_height_0__pin_42_lower, + output [0:0] right_width_0_height_0__pin_43_upper, + output [0:0] right_width_0_height_0__pin_43_lower, + output [0:0] right_width_0_height_0__pin_44_upper, + output [0:0] right_width_0_height_0__pin_44_lower, + output [0:0] right_width_0_height_0__pin_45_upper, + output [0:0] right_width_0_height_0__pin_45_lower, + output [0:0] right_width_0_height_0__pin_46_upper, + output [0:0] right_width_0_height_0__pin_46_lower, + output [0:0] right_width_0_height_0__pin_47_upper, + output [0:0] right_width_0_height_0__pin_47_lower, + output [0:0] right_width_0_height_0__pin_48_upper, + output [0:0] right_width_0_height_0__pin_48_lower, + output [0:0] right_width_0_height_0__pin_49_upper, + output [0:0] right_width_0_height_0__pin_49_lower, + output [0:0] bottom_width_0_height_0__pin_50_, + output [0:0] bottom_width_0_height_0__pin_51_, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0]; + assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0]; + assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0]; + assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0]; + assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0]; + assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0]; + assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0]; + assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0]; + assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0]; + assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0]; + assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0]; + assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0]; + assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0]; + assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0]; + assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0]; + assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + logical_tile_clb_mode_clb_ + logical_tile_clb_mode_clb__0 + ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }), + .clb_I0i(top_width_0_height_0__pin_3_[0]), + .clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }), + .clb_I1i(top_width_0_height_0__pin_7_[0]), + .clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }), + .clb_I2i(top_width_0_height_0__pin_11_[0]), + .clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }), + .clb_I3i(top_width_0_height_0__pin_15_[0]), + .clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }), + .clb_I4i(right_width_0_height_0__pin_19_[0]), + .clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }), + .clb_I5i(right_width_0_height_0__pin_23_[0]), + .clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }), + .clb_I6i(right_width_0_height_0__pin_27_[0]), + .clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }), + .clb_I7i(right_width_0_height_0__pin_31_[0]), + .clb_regin(top_width_0_height_0__pin_32_[0]), + .clb_sc_in(SC_IN_TOP), + .clb_clk(left_width_0_height_0__pin_52_[0]), + .ccff_head(ccff_head[0]), + .clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }), + .clb_regout(bottom_width_0_height_0__pin_50_[0]), + .clb_sc_out(SC_OUT_BOT), + .ccff_tail(ccff_tail[0]) + ); -// -// -// - assign right_width_0_height_0__pin_34_lower[0] = right_width_0_height_0__pin_34_upper[0]; - assign right_width_0_height_0__pin_35_lower[0] = right_width_0_height_0__pin_35_upper[0]; - assign right_width_0_height_0__pin_36_lower[0] = right_width_0_height_0__pin_36_upper[0]; - assign right_width_0_height_0__pin_37_lower[0] = right_width_0_height_0__pin_37_upper[0]; - assign right_width_0_height_0__pin_38_lower[0] = right_width_0_height_0__pin_38_upper[0]; - assign right_width_0_height_0__pin_39_lower[0] = right_width_0_height_0__pin_39_upper[0]; - assign right_width_0_height_0__pin_40_lower[0] = right_width_0_height_0__pin_40_upper[0]; - assign right_width_0_height_0__pin_41_lower[0] = right_width_0_height_0__pin_41_upper[0]; - assign bottom_width_0_height_0__pin_42_lower[0] = bottom_width_0_height_0__pin_42_upper[0]; - assign bottom_width_0_height_0__pin_43_lower[0] = bottom_width_0_height_0__pin_43_upper[0]; - assign bottom_width_0_height_0__pin_44_lower[0] = bottom_width_0_height_0__pin_44_upper[0]; - assign bottom_width_0_height_0__pin_45_lower[0] = bottom_width_0_height_0__pin_45_upper[0]; - assign bottom_width_0_height_0__pin_46_lower[0] = bottom_width_0_height_0__pin_46_upper[0]; - assign bottom_width_0_height_0__pin_47_lower[0] = bottom_width_0_height_0__pin_47_upper[0]; - assign bottom_width_0_height_0__pin_48_lower[0] = bottom_width_0_height_0__pin_48_upper[0]; - assign bottom_width_0_height_0__pin_49_lower[0] = bottom_width_0_height_0__pin_49_upper[0]; -// - - logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .clb_I0({right_width_0_height_0__pin_0_[0], right_width_0_height_0__pin_1_[0], right_width_0_height_0__pin_2_[0], right_width_0_height_0__pin_3_[0]}), - .clb_I1({right_width_0_height_0__pin_4_[0], right_width_0_height_0__pin_5_[0], right_width_0_height_0__pin_6_[0], right_width_0_height_0__pin_7_[0]}), - .clb_I2({right_width_0_height_0__pin_8_[0], right_width_0_height_0__pin_9_[0], right_width_0_height_0__pin_10_[0], right_width_0_height_0__pin_11_[0]}), - .clb_I3({right_width_0_height_0__pin_12_[0], right_width_0_height_0__pin_13_[0], right_width_0_height_0__pin_14_[0], right_width_0_height_0__pin_15_[0]}), - .clb_I4({bottom_width_0_height_0__pin_16_[0], bottom_width_0_height_0__pin_17_[0], bottom_width_0_height_0__pin_18_[0], bottom_width_0_height_0__pin_19_[0]}), - .clb_I5({bottom_width_0_height_0__pin_20_[0], bottom_width_0_height_0__pin_21_[0], bottom_width_0_height_0__pin_22_[0], bottom_width_0_height_0__pin_23_[0]}), - .clb_I6({bottom_width_0_height_0__pin_24_[0], bottom_width_0_height_0__pin_25_[0], bottom_width_0_height_0__pin_26_[0], bottom_width_0_height_0__pin_27_[0]}), - .clb_I7({bottom_width_0_height_0__pin_28_[0], bottom_width_0_height_0__pin_29_[0], bottom_width_0_height_0__pin_30_[0], bottom_width_0_height_0__pin_31_[0]}), - .clb_regin(top_width_0_height_0__pin_32_[0]), - .clb_scin(top_width_0_height_0__pin_33_[0]), - .clb_clk(left_width_0_height_0__pin_52_[0]), - .ccff_head(ccff_head[0]), - .clb_O({right_width_0_height_0__pin_34_upper[0], right_width_0_height_0__pin_35_upper[0], right_width_0_height_0__pin_36_upper[0], right_width_0_height_0__pin_37_upper[0], right_width_0_height_0__pin_38_upper[0], right_width_0_height_0__pin_39_upper[0], right_width_0_height_0__pin_40_upper[0], right_width_0_height_0__pin_41_upper[0], bottom_width_0_height_0__pin_42_upper[0], bottom_width_0_height_0__pin_43_upper[0], bottom_width_0_height_0__pin_44_upper[0], bottom_width_0_height_0__pin_45_upper[0], bottom_width_0_height_0__pin_46_upper[0], bottom_width_0_height_0__pin_47_upper[0], bottom_width_0_height_0__pin_48_upper[0], bottom_width_0_height_0__pin_49_upper[0]}), - .clb_regout(bottom_width_0_height_0__pin_50_[0]), - .clb_scout(bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(ccff_tail[0])); endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v index 654b409..2c819d1 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v @@ -11,34 +11,76 @@ // // module grid_io_bottom(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - top_width_0_height_0__pin_0_, - ccff_head, - top_width_0_height_0__pin_1_upper, - top_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + top_width_0_height_0__pin_0_, + top_width_0_height_0__pin_2_, + top_width_0_height_0__pin_4_, + top_width_0_height_0__pin_6_, + top_width_0_height_0__pin_8_, + top_width_0_height_0__pin_10_, + ccff_head, + top_width_0_height_0__pin_1_upper, + top_width_0_height_0__pin_1_lower, + top_width_0_height_0__pin_3_upper, + top_width_0_height_0__pin_3_lower, + top_width_0_height_0__pin_5_upper, + top_width_0_height_0__pin_5_lower, + top_width_0_height_0__pin_7_upper, + top_width_0_height_0__pin_7_lower, + top_width_0_height_0__pin_9_upper, + top_width_0_height_0__pin_9_lower, + top_width_0_height_0__pin_11_upper, + top_width_0_height_0__pin_11_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] top_width_0_height_0__pin_0_; // +input [0:0] top_width_0_height_0__pin_2_; +// +input [0:0] top_width_0_height_0__pin_4_; +// +input [0:0] top_width_0_height_0__pin_6_; +// +input [0:0] top_width_0_height_0__pin_8_; +// +input [0:0] top_width_0_height_0__pin_10_; +// input [0:0] ccff_head; // output [0:0] top_width_0_height_0__pin_1_upper; // output [0:0] top_width_0_height_0__pin_1_lower; // +output [0:0] top_width_0_height_0__pin_3_upper; +// +output [0:0] top_width_0_height_0__pin_3_lower; +// +output [0:0] top_width_0_height_0__pin_5_upper; +// +output [0:0] top_width_0_height_0__pin_5_lower; +// +output [0:0] top_width_0_height_0__pin_7_upper; +// +output [0:0] top_width_0_height_0__pin_7_lower; +// +output [0:0] top_width_0_height_0__pin_9_upper; +// +output [0:0] top_width_0_height_0__pin_9_lower; +// +output [0:0] top_width_0_height_0__pin_11_upper; +// +output [0:0] top_width_0_height_0__pin_11_lower; +// output [0:0] ccff_tail; // @@ -49,22 +91,81 @@ output [0:0] ccff_tail; // +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; // // // assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; + assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; + assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; + assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; + assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; + assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; // logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(top_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(top_width_0_height_0__pin_1_upper[0]), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .io_outpad(top_width_0_height_0__pin_2_[0]), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_3_upper[0]), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .io_outpad(top_width_0_height_0__pin_4_[0]), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_5_upper[0]), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .io_outpad(top_width_0_height_0__pin_6_[0]), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_7_upper[0]), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), + .io_outpad(top_width_0_height_0__pin_8_[0]), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_9_upper[0]), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), + .io_outpad(top_width_0_height_0__pin_10_[0]), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_11_upper[0]), .ccff_tail(ccff_tail[0])); endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v index 2426295..53ad4f9 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v @@ -11,25 +11,22 @@ // // module grid_io_left(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - right_width_0_height_0__pin_0_, - ccff_head, - right_width_0_height_0__pin_1_upper, - right_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + right_width_0_height_0__pin_0_, + ccff_head, + right_width_0_height_0__pin_1_upper, + right_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] right_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(right_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(right_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v index 2d402ca..5c65f69 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v @@ -11,25 +11,22 @@ // // module grid_io_right(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - left_width_0_height_0__pin_0_, - ccff_head, - left_width_0_height_0__pin_1_upper, - left_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + left_width_0_height_0__pin_0_, + ccff_head, + left_width_0_height_0__pin_1_upper, + left_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] left_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(left_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(left_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v index c21d0d6..15931d1 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v @@ -11,25 +11,22 @@ // // module grid_io_top(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - bottom_width_0_height_0__pin_0_, - ccff_head, - bottom_width_0_height_0__pin_1_upper, - bottom_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + bottom_width_0_height_0__pin_0_, + ccff_head, + bottom_width_0_height_0__pin_1_upper, + bottom_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] bottom_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(bottom_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v index 9b755b2..356dd66 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v @@ -14,20 +14,28 @@ module logical_tile_clb_mode_clb_(prog_clk, Test_en, clk, clb_I0, + clb_I0i, clb_I1, + clb_I1i, clb_I2, + clb_I2i, clb_I3, + clb_I3i, clb_I4, + clb_I4i, clb_I5, + clb_I5i, clb_I6, + clb_I6i, clb_I7, + clb_I7i, clb_regin, - clb_scin, + clb_sc_in, clb_clk, ccff_head, clb_O, clb_regout, - clb_scout, + clb_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -36,25 +44,41 @@ input [0:0] Test_en; // input [0:0] clk; // -input [0:3] clb_I0; +input [0:2] clb_I0; // -input [0:3] clb_I1; +input [0:0] clb_I0i; // -input [0:3] clb_I2; +input [0:2] clb_I1; // -input [0:3] clb_I3; +input [0:0] clb_I1i; // -input [0:3] clb_I4; +input [0:2] clb_I2; // -input [0:3] clb_I5; +input [0:0] clb_I2i; // -input [0:3] clb_I6; +input [0:2] clb_I3; // -input [0:3] clb_I7; +input [0:0] clb_I3i; +// +input [0:2] clb_I4; +// +input [0:0] clb_I4i; +// +input [0:2] clb_I5; +// +input [0:0] clb_I5i; +// +input [0:2] clb_I6; +// +input [0:0] clb_I6i; +// +input [0:2] clb_I7; +// +input [0:0] clb_I7i; // input [0:0] clb_regin; // -input [0:0] clb_scin; +input [0:0] clb_sc_in; // input [0:0] clb_clk; // @@ -64,25 +88,33 @@ output [0:15] clb_O; // output [0:0] clb_regout; // -output [0:0] clb_scout; +output [0:0] clb_sc_out; // output [0:0] ccff_tail; // -wire [0:3] clb_I0; -wire [0:3] clb_I1; -wire [0:3] clb_I2; -wire [0:3] clb_I3; -wire [0:3] clb_I4; -wire [0:3] clb_I5; -wire [0:3] clb_I6; -wire [0:3] clb_I7; +wire [0:2] clb_I0; +wire [0:0] clb_I0i; +wire [0:2] clb_I1; +wire [0:0] clb_I1i; +wire [0:2] clb_I2; +wire [0:0] clb_I2i; +wire [0:2] clb_I3; +wire [0:0] clb_I3i; +wire [0:2] clb_I4; +wire [0:0] clb_I4i; +wire [0:2] clb_I5; +wire [0:0] clb_I5i; +wire [0:2] clb_I6; +wire [0:0] clb_I6i; +wire [0:2] clb_I7; +wire [0:0] clb_I7i; wire [0:0] clb_regin; -wire [0:0] clb_scin; +wire [0:0] clb_sc_in; wire [0:0] clb_clk; wire [0:15] clb_O; wire [0:0] clb_regout; -wire [0:0] clb_scout; +wire [0:0] clb_sc_out; // @@ -149,34 +181,34 @@ wire [0:0] direct_interc_73_out; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out; wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; // // @@ -189,12 +221,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}), .fle_regin(direct_interc_22_out[0]), - .fle_scin(direct_interc_23_out[0]), + .fle_sc_in(direct_interc_23_out[0]), .fle_clk(direct_interc_24_out[0]), .ccff_head(ccff_head[0]), .fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( @@ -203,12 +235,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}), .fle_regin(direct_interc_29_out[0]), - .fle_scin(direct_interc_30_out[0]), + .fle_sc_in(direct_interc_30_out[0]), .fle_clk(direct_interc_31_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( @@ -217,12 +249,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}), .fle_regin(direct_interc_36_out[0]), - .fle_scin(direct_interc_37_out[0]), + .fle_sc_in(direct_interc_37_out[0]), .fle_clk(direct_interc_38_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( @@ -231,12 +263,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}), .fle_regin(direct_interc_43_out[0]), - .fle_scin(direct_interc_44_out[0]), + .fle_sc_in(direct_interc_44_out[0]), .fle_clk(direct_interc_45_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 ( @@ -245,12 +277,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}), .fle_regin(direct_interc_50_out[0]), - .fle_scin(direct_interc_51_out[0]), + .fle_sc_in(direct_interc_51_out[0]), .fle_clk(direct_interc_52_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 ( @@ -259,12 +291,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}), .fle_regin(direct_interc_57_out[0]), - .fle_scin(direct_interc_58_out[0]), + .fle_sc_in(direct_interc_58_out[0]), .fle_clk(direct_interc_59_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 ( @@ -273,12 +305,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}), .fle_regin(direct_interc_64_out[0]), - .fle_scin(direct_interc_65_out[0]), + .fle_sc_in(direct_interc_65_out[0]), .fle_clk(direct_interc_66_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( @@ -287,12 +319,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}), .fle_regin(direct_interc_71_out[0]), - .fle_scin(direct_interc_72_out[0]), + .fle_sc_in(direct_interc_72_out[0]), .fle_clk(direct_interc_73_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_7_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), .ccff_tail(ccff_tail[0])); direct_interc direct_interc_0_ ( @@ -364,11 +396,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(clb_regout[0])); direct_interc direct_interc_17_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_scout[0]), - .out(clb_scout[0])); + .in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), + .out(clb_sc_out[0])); direct_interc direct_interc_18_ ( - .in(clb_I0[0]), + .in(clb_I0[2]), .out(direct_interc_18_out[0])); direct_interc direct_interc_19_ ( @@ -376,11 +408,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_19_out[0])); direct_interc direct_interc_20_ ( - .in(clb_I0[2]), + .in(clb_I0[0]), .out(direct_interc_20_out[0])); direct_interc direct_interc_21_ ( - .in(clb_I0[3]), + .in(clb_I0i[0]), .out(direct_interc_21_out[0])); direct_interc direct_interc_22_ ( @@ -388,7 +420,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_22_out[0])); direct_interc direct_interc_23_ ( - .in(clb_scin[0]), + .in(clb_sc_in[0]), .out(direct_interc_23_out[0])); direct_interc direct_interc_24_ ( @@ -396,7 +428,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_24_out[0])); direct_interc direct_interc_25_ ( - .in(clb_I1[0]), + .in(clb_I1[2]), .out(direct_interc_25_out[0])); direct_interc direct_interc_26_ ( @@ -404,11 +436,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_26_out[0])); direct_interc direct_interc_27_ ( - .in(clb_I1[2]), + .in(clb_I1[0]), .out(direct_interc_27_out[0])); direct_interc direct_interc_28_ ( - .in(clb_I1[3]), + .in(clb_I1i[0]), .out(direct_interc_28_out[0])); direct_interc direct_interc_29_ ( @@ -416,7 +448,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_29_out[0])); direct_interc direct_interc_30_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), .out(direct_interc_30_out[0])); direct_interc direct_interc_31_ ( @@ -424,7 +456,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_31_out[0])); direct_interc direct_interc_32_ ( - .in(clb_I2[0]), + .in(clb_I2[2]), .out(direct_interc_32_out[0])); direct_interc direct_interc_33_ ( @@ -432,11 +464,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_33_out[0])); direct_interc direct_interc_34_ ( - .in(clb_I2[2]), + .in(clb_I2[0]), .out(direct_interc_34_out[0])); direct_interc direct_interc_35_ ( - .in(clb_I2[3]), + .in(clb_I2i[0]), .out(direct_interc_35_out[0])); direct_interc direct_interc_36_ ( @@ -444,7 +476,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_36_out[0])); direct_interc direct_interc_37_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), .out(direct_interc_37_out[0])); direct_interc direct_interc_38_ ( @@ -452,7 +484,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_38_out[0])); direct_interc direct_interc_39_ ( - .in(clb_I3[0]), + .in(clb_I3[2]), .out(direct_interc_39_out[0])); direct_interc direct_interc_40_ ( @@ -460,11 +492,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_40_out[0])); direct_interc direct_interc_41_ ( - .in(clb_I3[2]), + .in(clb_I3[0]), .out(direct_interc_41_out[0])); direct_interc direct_interc_42_ ( - .in(clb_I3[3]), + .in(clb_I3i[0]), .out(direct_interc_42_out[0])); direct_interc direct_interc_43_ ( @@ -472,7 +504,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_43_out[0])); direct_interc direct_interc_44_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), .out(direct_interc_44_out[0])); direct_interc direct_interc_45_ ( @@ -480,7 +512,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_45_out[0])); direct_interc direct_interc_46_ ( - .in(clb_I4[0]), + .in(clb_I4[2]), .out(direct_interc_46_out[0])); direct_interc direct_interc_47_ ( @@ -488,11 +520,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_47_out[0])); direct_interc direct_interc_48_ ( - .in(clb_I4[2]), + .in(clb_I4[0]), .out(direct_interc_48_out[0])); direct_interc direct_interc_49_ ( - .in(clb_I4[3]), + .in(clb_I4i[0]), .out(direct_interc_49_out[0])); direct_interc direct_interc_50_ ( @@ -500,7 +532,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_50_out[0])); direct_interc direct_interc_51_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), .out(direct_interc_51_out[0])); direct_interc direct_interc_52_ ( @@ -508,7 +540,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_52_out[0])); direct_interc direct_interc_53_ ( - .in(clb_I5[0]), + .in(clb_I5[2]), .out(direct_interc_53_out[0])); direct_interc direct_interc_54_ ( @@ -516,11 +548,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_54_out[0])); direct_interc direct_interc_55_ ( - .in(clb_I5[2]), + .in(clb_I5[0]), .out(direct_interc_55_out[0])); direct_interc direct_interc_56_ ( - .in(clb_I5[3]), + .in(clb_I5i[0]), .out(direct_interc_56_out[0])); direct_interc direct_interc_57_ ( @@ -528,7 +560,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_57_out[0])); direct_interc direct_interc_58_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), .out(direct_interc_58_out[0])); direct_interc direct_interc_59_ ( @@ -536,7 +568,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_59_out[0])); direct_interc direct_interc_60_ ( - .in(clb_I6[0]), + .in(clb_I6[2]), .out(direct_interc_60_out[0])); direct_interc direct_interc_61_ ( @@ -544,11 +576,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_61_out[0])); direct_interc direct_interc_62_ ( - .in(clb_I6[2]), + .in(clb_I6[0]), .out(direct_interc_62_out[0])); direct_interc direct_interc_63_ ( - .in(clb_I6[3]), + .in(clb_I6i[0]), .out(direct_interc_63_out[0])); direct_interc direct_interc_64_ ( @@ -556,7 +588,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_64_out[0])); direct_interc direct_interc_65_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), .out(direct_interc_65_out[0])); direct_interc direct_interc_66_ ( @@ -564,7 +596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_66_out[0])); direct_interc direct_interc_67_ ( - .in(clb_I7[0]), + .in(clb_I7[2]), .out(direct_interc_67_out[0])); direct_interc direct_interc_68_ ( @@ -572,11 +604,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_68_out[0])); direct_interc direct_interc_69_ ( - .in(clb_I7[2]), + .in(clb_I7[0]), .out(direct_interc_69_out[0])); direct_interc direct_interc_70_ ( - .in(clb_I7[3]), + .in(clb_I7i[0]), .out(direct_interc_70_out[0])); direct_interc direct_interc_71_ ( @@ -584,7 +616,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_71_out[0])); direct_interc direct_interc_72_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), .out(direct_interc_72_out[0])); direct_interc direct_interc_73_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v index b7b27e9..7eb2470 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v @@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle(prog_clk, clk, fle_in, fle_regin, - fle_scin, + fle_sc_in, fle_clk, ccff_head, fle_out, fle_regout, - fle_scout, + fle_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -33,7 +33,7 @@ input [0:3] fle_in; // input [0:0] fle_regin; // -input [0:0] fle_scin; +input [0:0] fle_sc_in; // input [0:0] fle_clk; // @@ -43,18 +43,18 @@ output [0:1] fle_out; // output [0:0] fle_regout; // -output [0:0] fle_scout; +output [0:0] fle_sc_out; // output [0:0] ccff_tail; // wire [0:3] fle_in; wire [0:0] fle_regin; -wire [0:0] fle_scin; +wire [0:0] fle_sc_in; wire [0:0] fle_clk; wire [0:1] fle_out; wire [0:0] fle_regout; -wire [0:0] fle_scout; +wire [0:0] fle_sc_out; // @@ -71,7 +71,7 @@ wire [0:0] direct_interc_8_out; wire [0:0] direct_interc_9_out; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; // // @@ -84,12 +84,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .clk(clk[0]), .fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}), .fabric_regin(direct_interc_8_out[0]), - .fabric_scin(direct_interc_9_out[0]), + .fabric_sc_in(direct_interc_9_out[0]), .fabric_clk(direct_interc_10_out[0]), .ccff_head(ccff_head[0]), .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]), .fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), - .fabric_scout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), + .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), .ccff_tail(ccff_tail[0])); direct_interc direct_interc_0_ ( @@ -105,8 +105,8 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .out(fle_regout[0])); direct_interc direct_interc_3_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), - .out(fle_scout[0])); + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), + .out(fle_sc_out[0])); direct_interc direct_interc_4_ ( .in(fle_in[0]), @@ -129,7 +129,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .out(direct_interc_8_out[0])); direct_interc direct_interc_9_ ( - .in(fle_scin[0]), + .in(fle_sc_in[0]), .out(direct_interc_9_out[0])); direct_interc direct_interc_10_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 0364910..047fb7b 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk, clk, fabric_in, fabric_regin, - fabric_scin, + fabric_sc_in, fabric_clk, ccff_head, fabric_out, fabric_regout, - fabric_scout, + fabric_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -33,7 +33,7 @@ input [0:3] fabric_in; // input [0:0] fabric_regin; // -input [0:0] fabric_scin; +input [0:0] fabric_sc_in; // input [0:0] fabric_clk; // @@ -43,18 +43,18 @@ output [0:1] fabric_out; // output [0:0] fabric_regout; // -output [0:0] fabric_scout; +output [0:0] fabric_sc_out; // output [0:0] ccff_tail; // wire [0:3] fabric_in; wire [0:0] fabric_regin; -wire [0:0] fabric_scin; +wire [0:0] fabric_sc_in; wire [0:0] fabric_clk; wire [0:1] fabric_out; wire [0:0] fabric_regout; -wire [0:0] fabric_scout; +wire [0:0] fabric_sc_out; // @@ -158,7 +158,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail; direct_interc direct_interc_1_ ( .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .out(fabric_scout[0])); + .out(fabric_sc_out[0])); direct_interc direct_interc_2_ ( .in(fabric_in[0]), @@ -177,7 +177,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail; .out(direct_interc_5_out[0])); direct_interc direct_interc_6_ ( - .in(fabric_scin[0]), + .in(fabric_sc_in[0]), .out(direct_interc_6_out[0])); direct_interc direct_interc_7_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v index 824e4d4..e484d05 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -46,7 +46,7 @@ wire [0:0] ff_clk; // // - sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( + sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .SCE(Test_en[0]), .CLK(clk[0]), .D(ff_D[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v index 247d7f4..ae105cb 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v @@ -11,10 +11,9 @@ // // module logical_tile_io_mode_io_(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, io_outpad, ccff_head, io_inpad, @@ -22,13 +21,11 @@ module logical_tile_io_mode_io_(prog_clk, // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] io_outpad; // @@ -58,10 +55,9 @@ wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .iopad_outpad(direct_interc_1_out[0]), .ccff_head(ccff_head[0]), .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v index a39f079..0d0c7f5 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v @@ -10,10 +10,9 @@ // module logical_tile_io_mode_physical__iopad(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, iopad_outpad, ccff_head, iopad_inpad, @@ -21,13 +20,11 @@ module logical_tile_io_mode_physical__iopad(prog_clk, // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] iopad_outpad; // @@ -47,29 +44,28 @@ wire [0:0] iopad_inpad; // -wire [0:0] GPIO_0_en; -wire [0:0] GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; +wire [0:0] EMBEDDED_IO_0_en; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; // // // // - GPIO GPIO_0_ ( - .A(gfpga_pad_GPIO_A[0]), - .IE(gfpga_pad_GPIO_IE[0]), - .OE(gfpga_pad_GPIO_OE[0]), - .Y(gfpga_pad_GPIO_Y[0]), - .in(iopad_outpad[0]), - .mem_out(GPIO_0_en[0]), - .out(iopad_inpad[0])); + EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .FPGA_OUT(iopad_outpad[0]), + .FPGA_DIR(EMBEDDED_IO_0_en[0]), + .FPGA_IN(iopad_inpad[0])); - GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), - .mem_out(GPIO_0_en[0]), - .mem_outb(GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); + .mem_out(EMBEDDED_IO_0_en[0]), + .mem_outb(EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v index 8be116b..7e6adb0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v @@ -1,534 +1,328 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__0_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_16_, - top_grid_pin_17_, - top_grid_pin_18_, - top_grid_pin_19_, - top_grid_pin_20_, - top_grid_pin_21_, - top_grid_pin_22_, - top_grid_pin_23_, - top_grid_pin_24_, - top_grid_pin_25_, - top_grid_pin_26_, - top_grid_pin_27_, - top_grid_pin_28_, - top_grid_pin_29_, - top_grid_pin_30_, - top_grid_pin_31_, - bottom_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_16_; -// -output [0:0] top_grid_pin_17_; -// -output [0:0] top_grid_pin_18_; -// -output [0:0] top_grid_pin_19_; -// -output [0:0] top_grid_pin_20_; -// -output [0:0] top_grid_pin_21_; -// -output [0:0] top_grid_pin_22_; -// -output [0:0] top_grid_pin_23_; -// -output [0:0] top_grid_pin_24_; -// -output [0:0] top_grid_pin_25_; -// -output [0:0] top_grid_pin_26_; -// -output [0:0] top_grid_pin_27_; -// -output [0:0] top_grid_pin_28_; -// -output [0:0] top_grid_pin_29_; -// -output [0:0] top_grid_pin_30_; -// -output [0:0] top_grid_pin_31_; -// -output [0:0] bottom_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__0_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_10_, + output [0:0] ccff_tail, + input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] top_width_0_height_0__pin_0_, + input [0:0] top_width_0_height_0__pin_2_, + input [0:0] top_width_0_height_0__pin_4_, + input [0:0] top_width_0_height_0__pin_6_, + input [0:0] top_width_0_height_0__pin_8_, + input [0:0] top_width_0_height_0__pin_10_, + output [0:0] top_width_0_height_0__pin_1_upper, + output [0:0] top_width_0_height_0__pin_1_lower, + output [0:0] top_width_0_height_0__pin_3_upper, + output [0:0] top_width_0_height_0__pin_3_lower, + output [0:0] top_width_0_height_0__pin_5_upper, + output [0:0] top_width_0_height_0__pin_5_lower, + output [0:0] top_width_0_height_0__pin_7_upper, + output [0:0] top_width_0_height_0__pin_7_lower, + output [0:0] top_width_0_height_0__pin_9_upper, + output [0:0] top_width_0_height_0__pin_9_lower, + output [0:0] top_width_0_height_0__pin_11_upper, + output [0:0] top_width_0_height_0__pin_11_lower, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire ccff_tail_mid; + wire [0:0] logical_tile_io_mode_io__0_ccff_tail; + wire [0:0] logical_tile_io_mode_io__1_ccff_tail; + wire [0:0] logical_tile_io_mode_io__2_ccff_tail; + wire [0:0] logical_tile_io_mode_io__3_ccff_tail; + wire [0:0] logical_tile_io_mode_io__4_ccff_tail; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; + assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; + assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; + assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; + assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; + assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + mux_tree_tapbuf_size10 + mux_top_ipin_1 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_16_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_2 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(top_grid_pin_17_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(top_grid_pin_20_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(top_grid_pin_21_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(top_grid_pin_24_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(top_grid_pin_25_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(top_grid_pin_28_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_5 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(top_grid_pin_29_[0])); - mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(bottom_grid_pin_0_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(top_grid_pin_18_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(top_grid_pin_19_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(top_grid_pin_22_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(top_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_1_upper[0]), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(top_grid_pin_23_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(top_grid_pin_26_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__1 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .io_outpad(top_width_0_height_0__pin_2_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_3_upper[0]), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(top_grid_pin_27_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(top_grid_pin_30_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__2 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .io_outpad(top_width_0_height_0__pin_4_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_5_upper[0]), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(top_grid_pin_31_[0])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__3 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .io_outpad(top_width_0_height_0__pin_6_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_7_upper[0]), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__4 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), + .io_outpad(top_width_0_height_0__pin_8_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_9_upper[0]), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__5 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), + .io_outpad(top_width_0_height_0__pin_10_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_11_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v index d3201ef..2c3eebd 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v @@ -1,515 +1,464 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__1_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_16_, - top_grid_pin_17_, - top_grid_pin_18_, - top_grid_pin_19_, - top_grid_pin_20_, - top_grid_pin_21_, - top_grid_pin_22_, - top_grid_pin_23_, - top_grid_pin_24_, - top_grid_pin_25_, - top_grid_pin_26_, - top_grid_pin_27_, - top_grid_pin_28_, - top_grid_pin_29_, - top_grid_pin_30_, - top_grid_pin_31_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_16_; -// -output [0:0] top_grid_pin_17_; -// -output [0:0] top_grid_pin_18_; -// -output [0:0] top_grid_pin_19_; -// -output [0:0] top_grid_pin_20_; -// -output [0:0] top_grid_pin_21_; -// -output [0:0] top_grid_pin_22_; -// -output [0:0] top_grid_pin_23_; -// -output [0:0] top_grid_pin_24_; -// -output [0:0] top_grid_pin_25_; -// -output [0:0] top_grid_pin_26_; -// -output [0:0] top_grid_pin_27_; -// -output [0:0] top_grid_pin_28_; -// -output [0:0] top_grid_pin_29_; -// -output [0:0] top_grid_pin_30_; -// -output [0:0] top_grid_pin_31_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__1_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_1_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_3_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_5_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_7_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_9_, + output [0:0] bottom_grid_pin_10_, + output [0:0] bottom_grid_pin_11_, + output [0:0] bottom_grid_pin_12_, + output [0:0] bottom_grid_pin_13_, + output [0:0] bottom_grid_pin_14_, + output [0:0] bottom_grid_pin_15_, + output [0:0] ccff_tail, + input CLB_SC_IN, + output CLB_SC_OUT, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign CLB_SC_OUT = CLB_SC_IN; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_3_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_16_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(top_grid_pin_17_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(top_grid_pin_20_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_7 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_7_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(top_grid_pin_21_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(top_grid_pin_24_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_8 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(top_grid_pin_25_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(top_grid_pin_28_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_11 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_11_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(top_grid_pin_29_[0])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_ipin_12 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(bottom_grid_pin_12_[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_ipin_15 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(bottom_grid_pin_15_[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(top_grid_pin_18_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(top_grid_pin_19_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(top_grid_pin_22_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(top_grid_pin_23_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(top_grid_pin_26_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(top_grid_pin_27_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(top_grid_pin_30_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(top_grid_pin_31_[0])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_top_ipin_1 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(bottom_grid_pin_1_[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_top_ipin_2 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_5 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(bottom_grid_pin_5_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_6 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_9 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(bottom_grid_pin_9_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_10 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_13 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(bottom_grid_pin_13_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_14 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(bottom_grid_pin_14_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v index 23694e7..4b0b6f0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v @@ -1,230 +1,508 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__2_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] top_grid_pin_0_, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_1_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_3_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_5_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_7_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_9_, + output [0:0] bottom_grid_pin_10_, + output [0:0] bottom_grid_pin_11_, + output [0:0] bottom_grid_pin_12_, + output [0:0] bottom_grid_pin_13_, + output [0:0] bottom_grid_pin_14_, + output [0:0] bottom_grid_pin_15_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] bottom_width_0_height_0__pin_0_, + output [0:0] bottom_width_0_height_0__pin_1_upper, + output [0:0] bottom_width_0_height_0__pin_1_lower, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + wire ccff_tail_mid; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_bottom_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(top_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_0_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_3_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_7 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_7_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_8 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_11 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(bottom_grid_pin_11_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_12 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(bottom_grid_pin_12_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_15 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(bottom_grid_pin_15_[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_1 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(bottom_grid_pin_1_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_2 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_5 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(bottom_grid_pin_5_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_6 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_9 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(bottom_grid_pin_9_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_10 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_13 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(bottom_grid_pin_13_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_14 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(bottom_grid_pin_14_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); + + + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(bottom_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v index 169d56d..a7f5a19 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v @@ -1,249 +1,102 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cby_0__1_(prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - right_grid_pin_52_, - left_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:19] chany_top_in; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chany_top_out; -// -output [0:0] right_grid_pin_52_; -// -output [0:0] left_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cby_0__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] left_grid_pin_0_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] right_width_0_height_0__pin_0_, + output [0:0] right_width_0_height_0__pin_1_upper, + output [0:0] right_width_0_height_0__pin_1_lower +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire ccff_tail_mid; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0]; + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(left_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); -// -// -// -// - assign chany_top_out[0] = chany_bottom_in[0]; -// -// -// - assign chany_top_out[1] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[2] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[4] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[8] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[12] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[15]; -// -// -// - assign chany_top_out[16] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[18]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[19]; -// -// -// - assign chany_bottom_out[0] = chany_top_in[0]; -// -// -// - assign chany_bottom_out[1] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[2] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[4] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[8] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[12] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[16] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[18]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_left_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(right_grid_pin_52_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(right_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(right_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(left_grid_pin_0_[0])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v index 72ba185..0c41972 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v @@ -1,534 +1,455 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cby_1__1_(prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - right_grid_pin_52_, - left_grid_pin_0_, - left_grid_pin_1_, - left_grid_pin_2_, - left_grid_pin_3_, - left_grid_pin_4_, - left_grid_pin_5_, - left_grid_pin_6_, - left_grid_pin_7_, - left_grid_pin_8_, - left_grid_pin_9_, - left_grid_pin_10_, - left_grid_pin_11_, - left_grid_pin_12_, - left_grid_pin_13_, - left_grid_pin_14_, - left_grid_pin_15_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:19] chany_top_in; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chany_top_out; -// -output [0:0] right_grid_pin_52_; -// -output [0:0] left_grid_pin_0_; -// -output [0:0] left_grid_pin_1_; -// -output [0:0] left_grid_pin_2_; -// -output [0:0] left_grid_pin_3_; -// -output [0:0] left_grid_pin_4_; -// -output [0:0] left_grid_pin_5_; -// -output [0:0] left_grid_pin_6_; -// -output [0:0] left_grid_pin_7_; -// -output [0:0] left_grid_pin_8_; -// -output [0:0] left_grid_pin_9_; -// -output [0:0] left_grid_pin_10_; -// -output [0:0] left_grid_pin_11_; -// -output [0:0] left_grid_pin_12_; -// -output [0:0] left_grid_pin_13_; -// -output [0:0] left_grid_pin_14_; -// -output [0:0] left_grid_pin_15_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cby_1__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] left_grid_pin_16_, + output [0:0] left_grid_pin_17_, + output [0:0] left_grid_pin_18_, + output [0:0] left_grid_pin_19_, + output [0:0] left_grid_pin_20_, + output [0:0] left_grid_pin_21_, + output [0:0] left_grid_pin_22_, + output [0:0] left_grid_pin_23_, + output [0:0] left_grid_pin_24_, + output [0:0] left_grid_pin_25_, + output [0:0] left_grid_pin_26_, + output [0:0] left_grid_pin_27_, + output [0:0] left_grid_pin_28_, + output [0:0] left_grid_pin_29_, + output [0:0] left_grid_pin_30_, + output [0:0] left_grid_pin_31_, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(left_grid_pin_16_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + mux_tree_tapbuf_size10 + mux_right_ipin_3 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_19_[0]) + ); -// -// -// -// - assign chany_top_out[0] = chany_bottom_in[0]; -// -// -// - assign chany_top_out[1] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[2] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[4] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[8] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[12] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[15]; -// -// -// - assign chany_top_out[16] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[18]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[19]; -// -// -// - assign chany_bottom_out[0] = chany_top_in[0]; -// -// -// - assign chany_bottom_out[1] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[2] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[4] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[8] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[12] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[16] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[18]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_left_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(right_grid_pin_52_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_4 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(left_grid_pin_20_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(left_grid_pin_0_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_1 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(left_grid_pin_1_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_7 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(left_grid_pin_23_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_4 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(left_grid_pin_4_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_5 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(left_grid_pin_5_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_8 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(left_grid_pin_24_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(left_grid_pin_8_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_9 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[14], chany_top_in[14]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(left_grid_pin_9_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_11 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(left_grid_pin_27_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_12 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(left_grid_pin_12_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_13 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[18], chany_top_in[18]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(left_grid_pin_13_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_12 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(left_grid_pin_28_[0]) + ); - mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_right_ipin_15 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(left_grid_pin_31_[0]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_right_ipin_2 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(left_grid_pin_2_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_3 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(left_grid_pin_3_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_6 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(left_grid_pin_6_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_7 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(left_grid_pin_7_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_10 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(left_grid_pin_10_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_11 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(left_grid_pin_11_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_14 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(left_grid_pin_14_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_15 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(left_grid_pin_15_[0])); - mux_tree_tapbuf_size8_mem mem_right_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_1 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(left_grid_pin_17_[0]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_2 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(left_grid_pin_18_[0]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_5 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(left_grid_pin_21_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_6 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(left_grid_pin_22_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_9 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(left_grid_pin_25_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_10 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(left_grid_pin_26_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_13 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(left_grid_pin_29_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_14 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(left_grid_pin_30_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v new file mode 100644 index 0000000..b4f8f45 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v @@ -0,0 +1,502 @@ + + +module cby_2__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] right_grid_pin_0_, + output [0:0] left_grid_pin_16_, + output [0:0] left_grid_pin_17_, + output [0:0] left_grid_pin_18_, + output [0:0] left_grid_pin_19_, + output [0:0] left_grid_pin_20_, + output [0:0] left_grid_pin_21_, + output [0:0] left_grid_pin_22_, + output [0:0] left_grid_pin_23_, + output [0:0] left_grid_pin_24_, + output [0:0] left_grid_pin_25_, + output [0:0] left_grid_pin_26_, + output [0:0] left_grid_pin_27_, + output [0:0] left_grid_pin_28_, + output [0:0] left_grid_pin_29_, + output [0:0] left_grid_pin_30_, + output [0:0] left_grid_pin_31_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] left_width_0_height_0__pin_0_, + output [0:0] left_width_0_height_0__pin_1_upper, + output [0:0] left_width_0_height_0__pin_1_lower +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + wire ccff_tail_mid; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0]; + + mux_tree_tapbuf_size10 + mux_left_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(right_grid_pin_0_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_16_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_3 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(left_grid_pin_19_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_4 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(left_grid_pin_20_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_7 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(left_grid_pin_23_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_8 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(left_grid_pin_24_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_11 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(left_grid_pin_27_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_12 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(left_grid_pin_28_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_15 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(left_grid_pin_31_[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_1 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(left_grid_pin_17_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_2 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(left_grid_pin_18_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_5 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(left_grid_pin_21_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_6 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(left_grid_pin_22_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_9 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(left_grid_pin_25_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_10 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(left_grid_pin_26_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_13 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(left_grid_pin_29_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_14 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(left_grid_pin_30_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); + + + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(left_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(left_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); + + +endmodule + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v index 4dabe79..520177c 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v @@ -1,456 +1,522 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__0_(prog_clk, - chany_top_in, - top_left_grid_pin_1_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - right_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_1_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:0] right_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_1_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_1_, + input [0:0] right_bottom_grid_pin_3_, + input [0:0] right_bottom_grid_pin_5_, + input [0:0] right_bottom_grid_pin_7_, + input [0:0] right_bottom_grid_pin_9_, + input [0:0] right_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + assign chanx_right_out[10] = chany_top_in[9]; + assign chanx_right_out[11] = chany_top_in[10]; + assign chanx_right_out[18] = chany_top_in[17]; + assign chanx_right_out[19] = chany_top_in[18]; + assign chany_top_out[19] = chanx_right_in[0]; + assign chany_top_out[1] = chanx_right_in[2]; + assign chany_top_out[3] = chanx_right_in[4]; + assign chany_top_out[5] = chanx_right_in[6]; + assign chany_top_out[6] = chanx_right_in[7]; + assign chany_top_out[7] = chanx_right_in[8]; + assign chany_top_out[8] = chanx_right_in[9]; + assign chany_top_out[9] = chanx_right_in[10]; + assign chany_top_out[10] = chanx_right_in[11]; + assign chany_top_out[11] = chanx_right_in[12]; + assign chany_top_out[13] = chanx_right_in[14]; + assign chany_top_out[14] = chanx_right_in[15]; + assign chany_top_out[15] = chanx_right_in[16]; + assign chany_top_out[16] = chanx_right_in[17]; + assign chany_top_out[17] = chanx_right_in[18]; + assign chany_top_out[18] = chanx_right_in[19]; + + mux_tree_tapbuf_size2 + mux_top_track_0 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[1] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + mux_tree_tapbuf_size2 + mux_top_track_4 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[3] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[2]) + ); -// -// -// -// - assign chanx_right_out[14] = chany_top_in[13]; -// -// -// - assign chanx_right_out[15] = chany_top_in[14]; -// -// -// - assign chanx_right_out[16] = chany_top_in[15]; -// -// -// - assign chanx_right_out[17] = chany_top_in[16]; -// -// -// - assign chanx_right_out[18] = chany_top_in[17]; -// -// -// - assign chanx_right_out[19] = chany_top_in[18]; -// -// -// - assign chany_top_out[19] = chanx_right_in[0]; -// -// -// - assign chany_top_out[1] = chanx_right_in[2]; -// -// -// - assign chany_top_out[3] = chanx_right_in[4]; -// -// -// - assign chany_top_out[5] = chanx_right_in[6]; -// -// -// - assign chany_top_out[6] = chanx_right_in[7]; -// -// -// - assign chany_top_out[7] = chanx_right_in[8]; -// -// -// - assign chany_top_out[8] = chanx_right_in[9]; -// -// -// - assign chany_top_out[9] = chanx_right_in[10]; -// -// -// - assign chany_top_out[10] = chanx_right_in[11]; -// -// -// - assign chany_top_out[11] = chanx_right_in[12]; -// -// -// - assign chany_top_out[13] = chanx_right_in[14]; -// -// -// - assign chany_top_out[14] = chanx_right_in[15]; -// -// -// - assign chany_top_out[15] = chanx_right_in[16]; -// -// -// - assign chany_top_out[16] = chanx_right_in[17]; -// -// -// - assign chany_top_out[17] = chanx_right_in[18]; -// -// -// - assign chany_top_out[18] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size2 mux_top_track_0 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[1]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size2 + mux_top_track_8 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[5] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size2 mux_top_track_4 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[3]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[2])); - mux_tree_tapbuf_size2 mux_top_track_8 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[5]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size2 + mux_top_track_24 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size2 mux_top_track_24 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[13]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[12])); - mux_tree_tapbuf_size2 mux_right_track_10 ( - .in({chany_top_in[4], right_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chanx_right_out[5])); + mux_tree_tapbuf_size2 + mux_right_track_8 + ( + .in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size2 mux_right_track_12 ( - .in({chany_top_in[5], right_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chanx_right_out[6])); - mux_tree_tapbuf_size2 mux_right_track_14 ( - .in({chany_top_in[6], right_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chanx_right_out[7])); + mux_tree_tapbuf_size2 + mux_right_track_10 + ( + .in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[5]) + ); - mux_tree_tapbuf_size2 mux_right_track_16 ( - .in({chany_top_in[7], right_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chanx_right_out[8])); - mux_tree_tapbuf_size2 mux_right_track_18 ( - .in({chany_top_in[8], right_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chanx_right_out[9])); + mux_tree_tapbuf_size2 + mux_right_track_12 + ( + .in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_right_out[6]) + ); - mux_tree_tapbuf_size2 mux_right_track_20 ( - .in({chany_top_in[9], right_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chanx_right_out[10])); - mux_tree_tapbuf_size2 mux_right_track_22 ( - .in({chany_top_in[10], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chanx_right_out[11])); + mux_tree_tapbuf_size2 + mux_right_track_14 + ( + .in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chanx_right_out[7]) + ); - mux_tree_tapbuf_size2 mux_right_track_26 ( - .in({chany_top_in[12], right_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chanx_right_out[13])); - mux_tree_tapbuf_size2_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_16 + ( + .in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); - mux_tree_tapbuf_size2_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_18 + ( + .in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); - mux_tree_tapbuf_size2_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_24 + ( + .in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_right_out[12]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); - mux_tree_tapbuf_size6 mux_right_track_4 ( - .in({chany_top_in[1], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); - mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_right_track_2 ( - .in({chany_top_in[0], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chanx_right_out[1])); + mux_tree_tapbuf_size2_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); - mux_tree_tapbuf_size5 mux_right_track_6 ( - .in({chany_top_in[2], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chanx_right_out[3])); - mux_tree_tapbuf_size5_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + mux_tree_tapbuf_size2_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); - mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_right_track_8 ( - .in({chany_top_in[3], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size2_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); - mux_tree_tapbuf_size3 mux_right_track_24 ( - .in({chany_top_in[11], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + mux_tree_tapbuf_size2_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_0 + ( + .in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_2 + ( + .in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_4 + ( + .in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_6 + ( + .in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v index ae0f810..dc3f1ab 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v @@ -1,658 +1,846 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__1_(prog_clk, - chany_top_in, - top_left_grid_pin_1_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - chany_bottom_in, - bottom_left_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - chany_bottom_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_1_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_1_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_1_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_4_sram; + wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_5_sram; + wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_6_sram; + wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_2_sram; + wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_3_sram; + wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_4_sram; + wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_3_sram; + wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_4_sram; + wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_5_sram; + wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_6_sram; + wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chanx_right_out[19] = right_bottom_grid_pin_41_[0]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + + mux_tree_tapbuf_size6 + mux_top_track_0 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_4_sram; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_5_sram; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_6_sram; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_4_sram; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_5_sram; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_6_sram; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + mux_tree_tapbuf_size6 + mux_top_track_4 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); -// -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_right_out[18] = chany_bottom_in[0]; -// -// -// - assign chanx_right_out[17] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chanx_right_out[16] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chanx_right_out[15] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chanx_right_out[14] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - mux_tree_tapbuf_size6 mux_top_track_0 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size6 + mux_top_track_8 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size6 mux_top_track_4 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_top_out[2])); - mux_tree_tapbuf_size6 mux_top_track_8 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size6 + mux_right_track_0 + ( + .in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({chany_top_in[2], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_right_out[0])); - mux_tree_tapbuf_size6 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size6 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size6 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size6 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + mux_tree_tapbuf_size6 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_top_track_2 ( - .in({chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_top_out[1])); + mux_tree_tapbuf_size6_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_top_track_16 ( - .in({chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_top_out[8])); - mux_tree_tapbuf_size5 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size6_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size5 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), - .out(chany_bottom_out[12])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - mux_tree_tapbuf_size5_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - mux_tree_tapbuf_size5_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); - mux_tree_tapbuf_size4 mux_top_track_24 ( - .in({chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_top_out[12])); + mux_tree_tapbuf_size5 + mux_top_track_2 + ( + .in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); - mux_tree_tapbuf_size4 mux_top_track_32 ( - .in({chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_top_out[16])); - mux_tree_tapbuf_size4 mux_right_track_8 ( - .in({chany_top_in[7:8], right_top_grid_pin_42_[0], chany_bottom_in[8]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size5 + mux_top_track_16 + ( + .in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size4 mux_right_track_10 ( - .in({chany_top_in[9], chany_top_in[11], right_top_grid_pin_43_[0], chany_bottom_in[9]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_right_out[5])); - mux_tree_tapbuf_size4 mux_right_track_12 ( - .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_44_[0], chany_bottom_in[10]}), - .sram(mux_tree_tapbuf_size4_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), - .out(chanx_right_out[6])); + mux_tree_tapbuf_size5 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size4 mux_right_track_14 ( - .in({chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], chany_bottom_in[12]}), - .sram(mux_tree_tapbuf_size4_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), - .out(chanx_right_out[7])); - mux_tree_tapbuf_size4 mux_right_track_24 ( - .in({chany_top_in[18], right_top_grid_pin_42_[0], chany_bottom_in[18:19]}), - .sram(mux_tree_tapbuf_size4_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), - .out(chanx_right_out[12])); + mux_tree_tapbuf_size5 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size4_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + mux_tree_tapbuf_size5 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_right_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_right_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])); - mux_tree_tapbuf_size7 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[4], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chanx_right_out[1])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[5], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[5]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size7 mux_right_track_6 ( - .in({chany_top_in[3], chany_top_in[6], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[6]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chanx_right_out[3])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_right_track_16 ( - .in({chany_top_in[13], right_top_grid_pin_46_[0], chany_bottom_in[13]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[8])); + mux_tree_tapbuf_size4 + mux_top_track_24 + ( + .in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size3 mux_right_track_18 ( - .in({chany_top_in[14], right_top_grid_pin_47_[0], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_right_out[9])); - mux_tree_tapbuf_size3 mux_right_track_20 ( - .in({chany_top_in[16], right_top_grid_pin_48_[0], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_right_out[10])); + mux_tree_tapbuf_size4 + mux_top_track_32 + ( + .in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[16]) + ); - mux_tree_tapbuf_size3 mux_right_track_22 ( - .in({chany_top_in[17], right_top_grid_pin_49_[0], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_right_out[11])); - mux_tree_tapbuf_size3 mux_bottom_track_33 ( - .in({chany_top_in[10], chanx_right_in[6], chanx_right_in[13]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size4 + mux_right_track_8 + ( + .in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_right_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + mux_tree_tapbuf_size4 + mux_right_track_10 + ( + .in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[5]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + mux_tree_tapbuf_size4 + mux_right_track_12 + ( + .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_right_out[6]) + ); - mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - mux_tree_tapbuf_size2 mux_right_track_26 ( - .in({right_top_grid_pin_43_[0], chany_bottom_in[15]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chanx_right_out[13])); + mux_tree_tapbuf_size4 + mux_right_track_14 + ( + .in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_right_out[7]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_24 + ( + .in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_6 + ( + .in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_16 + ( + .in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_18 + ( + .in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_20 + ( + .in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_right_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_22 + ( + .in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_right_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_36 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[18]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_36 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v index 62bac18..6d4a63a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v @@ -1,312 +1,623 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__2_(prog_clk, - chanx_right_in, - right_top_grid_pin_1_, - chany_bottom_in, - bottom_left_grid_pin_1_, - ccff_head, - chanx_right_out, - chany_bottom_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_right_in, + input [0:0] right_top_grid_pin_1_, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_1_, + input [0:0] ccff_head, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + assign chany_bottom_out[18] = chanx_right_in[0]; + assign chany_bottom_out[17] = chanx_right_in[1]; + assign chany_bottom_out[16] = chanx_right_in[2]; + assign chany_bottom_out[15] = chanx_right_in[3]; + assign chany_bottom_out[14] = chanx_right_in[4]; + assign chany_bottom_out[13] = chanx_right_in[5]; + assign chany_bottom_out[11] = chanx_right_in[7]; + assign chany_bottom_out[10] = chanx_right_in[8]; + assign chany_bottom_out[9] = chanx_right_in[9]; + assign chany_bottom_out[8] = chanx_right_in[10]; + assign chany_bottom_out[7] = chanx_right_in[11]; + assign chany_bottom_out[6] = chanx_right_in[12]; + assign chany_bottom_out[5] = chanx_right_in[13]; + assign chany_bottom_out[3] = chanx_right_in[15]; + assign chany_bottom_out[1] = chanx_right_in[17]; + assign chany_bottom_out[19] = chanx_right_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size6 + mux_right_track_0 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + mux_tree_tapbuf_size6 + mux_right_track_4 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); -// -// -// -// - assign chany_bottom_out[18] = chanx_right_in[0]; -// -// -// - assign chany_bottom_out[17] = chanx_right_in[1]; -// -// -// - assign chany_bottom_out[16] = chanx_right_in[2]; -// -// -// - assign chany_bottom_out[15] = chanx_right_in[3]; -// -// -// - assign chany_bottom_out[14] = chanx_right_in[4]; -// -// -// - assign chany_bottom_out[13] = chanx_right_in[5]; -// -// -// - assign chany_bottom_out[11] = chanx_right_in[7]; -// -// -// - assign chany_bottom_out[10] = chanx_right_in[8]; -// -// -// - assign chany_bottom_out[9] = chanx_right_in[9]; -// -// -// - assign chany_bottom_out[8] = chanx_right_in[10]; -// -// -// - assign chany_bottom_out[7] = chanx_right_in[11]; -// -// -// - assign chany_bottom_out[6] = chanx_right_in[12]; -// -// -// - assign chany_bottom_out[5] = chanx_right_in[13]; -// -// -// - assign chany_bottom_out[3] = chanx_right_in[15]; -// -// -// - assign chany_bottom_out[1] = chanx_right_in[17]; -// -// -// - assign chany_bottom_out[19] = chanx_right_in[19]; -// -// -// - assign chanx_right_out[18] = chany_bottom_in[0]; -// -// -// - assign chanx_right_out[17] = chany_bottom_in[1]; -// -// -// - assign chanx_right_out[16] = chany_bottom_in[2]; -// -// -// - assign chanx_right_out[15] = chany_bottom_in[3]; -// -// -// - assign chanx_right_out[14] = chany_bottom_in[4]; -// -// -// - assign chanx_right_out[13] = chany_bottom_in[5]; -// -// -// - assign chanx_right_out[11] = chany_bottom_in[7]; -// -// -// - assign chanx_right_out[10] = chany_bottom_in[8]; -// -// -// - assign chanx_right_out[9] = chany_bottom_in[9]; -// -// -// - assign chanx_right_out[8] = chany_bottom_in[10]; -// -// -// - assign chanx_right_out[7] = chany_bottom_in[11]; -// -// -// - assign chanx_right_out[6] = chany_bottom_in[12]; -// -// -// - assign chanx_right_out[5] = chany_bottom_in[13]; -// -// -// - assign chanx_right_out[3] = chany_bottom_in[15]; -// -// -// - assign chanx_right_out[1] = chany_bottom_in[17]; -// -// -// - assign chanx_right_out[19] = chany_bottom_in[19]; -// -// -// - mux_tree_tapbuf_size2 mux_right_track_0 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size6_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_right_track_4 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size2 mux_right_track_8 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size6_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_right_track_24 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[6]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size2 mux_bottom_track_1 ( - .in({chanx_right_in[18], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size5 + mux_right_track_2 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_5 ( - .in({chanx_right_in[16], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size2 mux_bottom_track_9 ( - .in({chanx_right_in[14], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size5 + mux_right_track_6 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_25 ( - .in({chanx_right_in[6], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size2_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size5_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size5_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size3 + mux_right_track_8 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size3 + mux_right_track_24 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_10 + ( + .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_12 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_14 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_16 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_18 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_20 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_22 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_right_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_36 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_right_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_38 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_right_out[19]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_1 + ( + .in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chany_bottom_out[0]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_5 + ( + .in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chany_bottom_out[2]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_9 + ( + .in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_25 + ( + .in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_36 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_38 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v index 2ed68b1..2b08218 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v @@ -1,770 +1,747 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__0_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - right_bottom_grid_pin_1_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - left_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:0] right_bottom_grid_pin_1_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] left_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:3] mux_tree_tapbuf_size14_0_sram; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size14_1_sram; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_7_sram; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_4_sram; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_5_sram; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_6_sram; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:3] mux_tree_tapbuf_size9_0_sram; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size9_1_sram; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; - -// -// -// -// - assign chany_top_out[13] = top_left_grid_pin_35_[0]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - - mux_tree_tapbuf_size8 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size8 mux_right_track_8 ( - .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], right_bottom_grid_pin_1_[0], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size8 mux_left_track_3 ( - .in({chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size8 mux_left_track_9 ( - .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size8_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - - mux_tree_tapbuf_size7 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size7 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size7 mux_top_track_6 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_top_out[3])); - - mux_tree_tapbuf_size7 mux_right_track_16 ( - .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size7 mux_right_track_24 ( - .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), - .out(chanx_right_out[12])); - - mux_tree_tapbuf_size7 mux_left_track_17 ( - .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size7 mux_left_track_25 ( - .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size7_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_top_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); - - mux_tree_tapbuf_size4 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_top_out[4])); - - mux_tree_tapbuf_size4 mux_top_track_10 ( - .in({top_left_grid_pin_35_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_top_out[5])); - - mux_tree_tapbuf_size4_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_top_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_top_track_12 ( - .in({top_left_grid_pin_36_[0], chanx_right_in[10], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_top_out[6])); - - mux_tree_tapbuf_size3 mux_top_track_14 ( - .in({top_left_grid_pin_37_[0], chanx_right_in[12], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_top_out[7])); - - mux_tree_tapbuf_size3 mux_top_track_16 ( - .in({top_left_grid_pin_38_[0], chanx_right_in[13], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chany_top_out[8])); - - mux_tree_tapbuf_size3 mux_top_track_18 ( - .in({top_left_grid_pin_39_[0], chanx_right_in[14], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chany_top_out[9])); - - mux_tree_tapbuf_size3 mux_top_track_20 ( - .in({top_left_grid_pin_40_[0], chanx_right_in[16], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_top_out[10])); - - mux_tree_tapbuf_size3 mux_top_track_22 ( - .in({top_left_grid_pin_41_[0], chanx_right_in[17], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), - .out(chany_top_out[11])); - - mux_tree_tapbuf_size3 mux_top_track_24 ( - .in({top_left_grid_pin_34_[0], chanx_right_in[18], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), - .out(chany_top_out[12])); - - mux_tree_tapbuf_size3 mux_top_track_38 ( - .in({top_left_grid_pin_41_[0], chanx_right_in[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size3_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), - .out(chany_top_out[19])); - - mux_tree_tapbuf_size3_mem mem_top_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_38 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); - - mux_tree_tapbuf_size2 mux_top_track_28 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[14])); - - mux_tree_tapbuf_size2 mux_top_track_30 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[15])); - - mux_tree_tapbuf_size2 mux_top_track_32 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[16])); - - mux_tree_tapbuf_size2 mux_top_track_34 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[17])); - - mux_tree_tapbuf_size2 mux_top_track_36 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_top_out[18])); - - mux_tree_tapbuf_size2_mem mem_top_track_28 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_30 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_34 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_36 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size9 mux_right_track_0 ( - .in({chany_top_in[6], chany_top_in[13], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size9 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size9_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size9_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); - - mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3])); - - mux_tree_tapbuf_size14 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], right_bottom_grid_pin_1_[0], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size14 mux_left_track_5 ( - .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); - - mux_tree_tapbuf_size14_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); - - mux_tree_tapbuf_size6 mux_right_track_32 ( - .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[16])); - - mux_tree_tapbuf_size6 mux_left_track_33 ( - .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_left_out[16])); - - mux_tree_tapbuf_size6_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size10 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size10_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + +module sb_1__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_1_, + input [0:0] right_bottom_grid_pin_3_, + input [0:0] right_bottom_grid_pin_5_, + input [0:0] right_bottom_grid_pin_7_, + input [0:0] right_bottom_grid_pin_9_, + input [0:0] right_bottom_grid_pin_11_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_1_, + input [0:0] left_bottom_grid_pin_3_, + input [0:0] left_bottom_grid_pin_5_, + input [0:0] left_bottom_grid_pin_7_, + input [0:0] left_bottom_grid_pin_9_, + input [0:0] left_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size11_0_sram; + wire [0:3] mux_tree_tapbuf_size11_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size11_1_sram; + wire [0:3] mux_tree_tapbuf_size11_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_5_sram; + wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_6_sram; + wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_7_sram; + wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_8_sram; + wire [0:2] mux_tree_tapbuf_size7_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + assign chany_top_out[13] = top_left_grid_pin_43_[0]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chany_top_out[18] = chanx_left_in[3]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chany_top_out[17] = chanx_left_in[7]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chany_top_out[16] = chanx_left_in[11]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chany_top_out[15] = chanx_left_in[15]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + assign chany_top_out[14] = chanx_left_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size8 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size8 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_6 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_top_out[3]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_0 + ( + .in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_8 + ( + .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_right_out[4]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_16 + ( + .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_3 + ( + .in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_9 + ( + .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size7_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_17 + ( + .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size7_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_8_sram_inv[0:2]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_8_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_top_track_10 + ( + .in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[5]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_12 + ( + .in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[6]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_14 + ( + .in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[7]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_16 + ( + .in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_18 + ( + .in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_20 + ( + .in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_22 + ( + .in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_24 + ( + .in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_top_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_38 + ( + .in({ chanx_right_in[0], chanx_left_in[1] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_38 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size11 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size11_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size11_0_sram_inv[0:3]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size11 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size11_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size11_1_sram_inv[0:3]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size11_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size11_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size11_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size11_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size6 + mux_right_track_24 + ( + .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size6 + mux_left_track_25 + ( + .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size6_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_right_track_32 + ( + .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size5 + mux_left_track_33 + ( + .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size5_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v index 3e6c226..0296f7a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v @@ -1,814 +1,775 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__1_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - chany_bottom_in, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - ccff_head, - chany_top_out, - chanx_right_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_1__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_10_sram; + wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_11_sram; + wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_9_sram; + wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; + wire [0:3] mux_tree_tapbuf_size12_0_sram; + wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_1_sram; + wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_2_sram; + wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_3_sram; + wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_4_sram; + wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_5_sram; + wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_6_sram; + wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_7_sram; + wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire [0:4] mux_tree_tapbuf_size16_0_sram; + wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_1_sram; + wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_2_sram; + wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_3_sram; + wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + + mux_tree_tapbuf_size12 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_10_sram; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_11_sram; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_9_sram; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; -wire [0:3] mux_tree_tapbuf_size12_0_sram; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_1_sram; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_2_sram; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_3_sram; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_4_sram; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_5_sram; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_6_sram; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_7_sram; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; -wire [0:4] mux_tree_tapbuf_size16_0_sram; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_1_sram; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_2_sram; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_3_sram; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + mux_tree_tapbuf_size12 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), + .out(chany_top_out[1]) + ); -// -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - mux_tree_tapbuf_size12 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size12 + mux_right_track_0 + ( + .in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), + .out(chanx_right_out[0]) + ); - mux_tree_tapbuf_size12 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size12_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), - .out(chany_top_out[1])); - mux_tree_tapbuf_size12 mux_right_track_0 ( - .in({chany_top_in[2], chany_top_in[12], chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size12 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); - mux_tree_tapbuf_size12 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[4], chany_top_in[13], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size12_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), - .out(chanx_right_out[1])); - mux_tree_tapbuf_size12 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size12 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), + .out(chany_bottom_out[0]) + ); - mux_tree_tapbuf_size12 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size12_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), - .out(chany_bottom_out[1])); - mux_tree_tapbuf_size12 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size12_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), - .out(chanx_left_out[0])); + mux_tree_tapbuf_size12 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size12 mux_left_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size12_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), - .out(chanx_left_out[1])); - mux_tree_tapbuf_size12_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3])); + mux_tree_tapbuf_size12 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size12_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3])); + mux_tree_tapbuf_size12 + mux_left_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size12_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3])); + mux_tree_tapbuf_size12_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size12_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3])); + mux_tree_tapbuf_size12_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size12_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3])); - mux_tree_tapbuf_size16 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15]}), - .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), - .out(chany_top_out[2])); + mux_tree_tapbuf_size12_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[5], chany_top_in[14], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size16 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size16_2_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), - .out(chany_bottom_out[2])); + mux_tree_tapbuf_size12_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16 mux_left_track_5 ( - .in({chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size16_3_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size16_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4])); + mux_tree_tapbuf_size12_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4])); - mux_tree_tapbuf_size16_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4])); + mux_tree_tapbuf_size12_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4])); - mux_tree_tapbuf_size10 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size12_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_top_track_16 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(chany_top_out[8])); - mux_tree_tapbuf_size10 mux_top_track_24 ( - .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(chany_top_out[12])); + mux_tree_tapbuf_size12_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_right_track_8 ( - .in({chany_top_in[3], chany_top_in[6], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(chanx_right_out[4])); - mux_tree_tapbuf_size10 mux_right_track_16 ( - .in({chany_top_in[7:8], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(chanx_right_out[8])); + mux_tree_tapbuf_size16 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }), + .sram(mux_tree_tapbuf_size16_0_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), + .out(chany_top_out[2]) + ); - mux_tree_tapbuf_size10 mux_right_track_24 ( - .in({chany_top_in[9], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size10 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size16 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size16_1_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), + .out(chanx_right_out[2]) + ); - mux_tree_tapbuf_size10 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size10 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[9], chanx_left_in[18:19]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(chany_bottom_out[12])); + mux_tree_tapbuf_size16 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size16_2_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size10 mux_left_track_9 ( - .in({chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), - .out(chanx_left_out[4])); - mux_tree_tapbuf_size10 mux_left_track_17 ( - .in({chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), - .out(chanx_left_out[8])); + mux_tree_tapbuf_size16 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size16_3_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size10 mux_left_track_25 ( - .in({chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), - .out(chanx_left_out[12])); - mux_tree_tapbuf_size10_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size10_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_track_16 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size10_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3])); - mux_tree_tapbuf_size7 mux_top_track_32 ( - .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[16])); + mux_tree_tapbuf_size10 + mux_top_track_24 + ( + .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size7 mux_right_track_32 ( - .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chanx_right_out[16])); - mux_tree_tapbuf_size7 mux_bottom_track_33 ( - .in({chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size10 + mux_right_track_8 + ( + .in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size7 mux_left_track_33 ( - .in({chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_left_out[16])); - mux_tree_tapbuf_size7_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + mux_tree_tapbuf_size10 + mux_right_track_16 + ( + .in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(chanx_right_out[8]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + mux_tree_tapbuf_size10 + mux_right_track_24 + ( + .in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(chany_bottom_out[8]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_9 + ( + .in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size10_9_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_17 + ( + .in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size10_10_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_25 + ( + .in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size10_11_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_32 + ( + .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_32 + ( + .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_33 + ( + .in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v index 0897208..5253fe0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v @@ -1,734 +1,753 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__2_(prog_clk, - chanx_right_in, - right_top_grid_pin_1_, - chany_bottom_in, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_1_, - ccff_head, - chanx_right_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_4_sram; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_5_sram; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_6_sram; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; - -// -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size6 mux_right_track_4 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size6 mux_right_track_8 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size6 mux_left_track_5 ( - .in({chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size6 mux_left_track_9 ( - .in({chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); - - mux_tree_tapbuf_size5 mux_right_track_2 ( - .in({chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size5 mux_right_track_16 ( - .in({chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size5 mux_right_track_24 ( - .in({chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chanx_right_out[12])); - - mux_tree_tapbuf_size5 mux_left_track_1 ( - .in({chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size5 mux_left_track_3 ( - .in({chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size5 mux_left_track_17 ( - .in({chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size5_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_5_sram_inv[0:2]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size5 mux_left_track_25 ( - .in({chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size5_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_6_sram_inv[0:2]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size5_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_5_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_6_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_right_track_32 ( - .in({chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[16])); - - mux_tree_tapbuf_size3 mux_bottom_track_13 ( - .in({chanx_right_in[10], bottom_left_grid_pin_36_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_bottom_out[6])); - - mux_tree_tapbuf_size3 mux_bottom_track_15 ( - .in({chanx_right_in[12], bottom_left_grid_pin_37_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chany_bottom_out[7])); - - mux_tree_tapbuf_size3 mux_bottom_track_17 ( - .in({chanx_right_in[13], bottom_left_grid_pin_38_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chany_bottom_out[8])); - - mux_tree_tapbuf_size3 mux_bottom_track_19 ( - .in({chanx_right_in[14], bottom_left_grid_pin_39_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_bottom_out[9])); - - mux_tree_tapbuf_size3 mux_bottom_track_21 ( - .in({chanx_right_in[16], bottom_left_grid_pin_40_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), - .out(chany_bottom_out[10])); - - mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in({chanx_right_in[17], bottom_left_grid_pin_41_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), - .out(chany_bottom_out[11])); - - mux_tree_tapbuf_size3_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); - - mux_tree_tapbuf_size7 mux_bottom_track_1 ( - .in({chanx_right_in[2], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_bottom_out[0])); - - mux_tree_tapbuf_size7 mux_bottom_track_3 ( - .in({chanx_right_in[4], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_bottom_out[1])); - - mux_tree_tapbuf_size7 mux_bottom_track_5 ( - .in({chanx_right_in[5], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[5], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[2])); - - mux_tree_tapbuf_size7 mux_bottom_track_7 ( - .in({chanx_right_in[6], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[6], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chany_bottom_out[3])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); - - mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in({chanx_right_in[8], bottom_left_grid_pin_34_[0], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_bottom_out[4])); - - mux_tree_tapbuf_size4 mux_bottom_track_11 ( - .in({chanx_right_in[9], bottom_left_grid_pin_35_[0], chanx_left_in[9], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_bottom_out[5])); - - mux_tree_tapbuf_size4 mux_bottom_track_25 ( - .in({chanx_right_in[18:19], bottom_left_grid_pin_34_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chany_bottom_out[12])); - - mux_tree_tapbuf_size4 mux_left_track_33 ( - .in({chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_left_out[16])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); - - mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in({chanx_right_in[15], bottom_left_grid_pin_35_[0]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_bottom_out[13])); - - mux_tree_tapbuf_size2 mux_bottom_track_29 ( - .in({chanx_right_in[11], bottom_left_grid_pin_36_[0]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_bottom_out[14])); - - mux_tree_tapbuf_size2 mux_bottom_track_31 ( - .in({chanx_right_in[7], bottom_left_grid_pin_37_[0]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_bottom_out[15])); - - mux_tree_tapbuf_size2 mux_bottom_track_33 ( - .in({chanx_right_in[3], bottom_left_grid_pin_38_[0]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_bottom_out[16])); - - mux_tree_tapbuf_size2 mux_bottom_track_35 ( - .in({chanx_right_in[1], bottom_left_grid_pin_39_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[17])); - - mux_tree_tapbuf_size2 mux_bottom_track_37 ( - .in({chanx_right_in[0], bottom_left_grid_pin_40_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[18])); - - mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in({bottom_left_grid_pin_41_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[19])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + +module sb_1__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_right_in, + input [0:0] right_top_grid_pin_1_, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_top_grid_pin_1_, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:3] mux_tree_tapbuf_size14_0_sram; + wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size14_1_sram; + wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_5_sram; + wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_7_sram; + wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:3] mux_tree_tapbuf_size9_0_sram; + wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size9_1_sram; + wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size9_2_sram; + wire [0:3] mux_tree_tapbuf_size9_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; + assign chany_bottom_out[18] = chanx_right_in[0]; + assign chany_bottom_out[17] = chanx_right_in[1]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chany_bottom_out[16] = chanx_right_in[3]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chany_bottom_out[15] = chanx_right_in[7]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chany_bottom_out[14] = chanx_right_in[11]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chany_bottom_out[19] = chanx_left_in[0]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_right_track_0 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9 + mux_right_track_2 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size9 + mux_left_track_1 + ( + .in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size9 + mux_left_track_3 + ( + .in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size9_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size9_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size14 + mux_right_track_4 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size14 + mux_left_track_5 + ( + .in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size14_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size14_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_right_track_8 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chanx_right_out[4]) + ); + + + mux_tree_tapbuf_size8 + mux_left_track_9 + ( + .in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_16 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_24 + ( + .in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_1 + ( + .in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_3 + ( + .in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_5 + ( + .in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_7 + ( + .in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chany_bottom_out[3]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_17 + ( + .in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_25 + ( + .in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size7_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size5_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_9 + ( + .in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_11 + ( + .in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_bottom_out[5]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_25 + ( + .in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_13 + ( + .in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[6]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_15 + ( + .in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[7]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_17 + ( + .in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_bottom_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_19 + ( + .in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_bottom_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_21 + ( + .in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_23 + ( + .in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_bottom_out[11]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_27 + ( + .in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[13]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size6 + mux_left_track_33 + ( + .in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size6_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v index 07d171b..e2a146e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v @@ -1,672 +1,760 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__0_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - top_right_grid_pin_1_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - left_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:0] top_right_grid_pin_1_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] left_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_12_sram; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_13_sram; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_14_sram; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_15_sram; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_16_sram; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_17_sram; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_18_sram; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_19_sram; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_20_sram; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_21_sram; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; - -// -// -// -// - assign chanx_left_out[19] = chany_top_in[1]; -// -// -// - assign chanx_left_out[18] = chany_top_in[2]; -// -// -// - assign chanx_left_out[17] = chany_top_in[3]; -// -// -// - assign chanx_left_out[16] = chany_top_in[4]; -// -// -// - assign chanx_left_out[15] = chany_top_in[5]; -// -// -// - assign chanx_left_out[14] = chany_top_in[6]; -// -// -// - - mux_tree_tapbuf_size6 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size6 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size6 mux_left_track_1 ( - .in({chany_top_in[0], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size6 mux_left_track_5 ( - .in({chany_top_in[18], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size6_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); - - mux_tree_tapbuf_size5 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size5 mux_top_track_6 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_top_out[3])); - - mux_tree_tapbuf_size5 mux_left_track_3 ( - .in({chany_top_in[19], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size5 mux_left_track_7 ( - .in({chany_top_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chanx_left_out[3])); - - mux_tree_tapbuf_size5_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_top_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_top_out[4])); - - mux_tree_tapbuf_size3 mux_top_track_24 ( - .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_top_out[12])); - - mux_tree_tapbuf_size3 mux_left_track_9 ( - .in({chany_top_in[16], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size3 mux_left_track_25 ( - .in({chany_top_in[8], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size3_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2 mux_top_track_10 ( - .in({top_left_grid_pin_35_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[5])); - - mux_tree_tapbuf_size2 mux_top_track_12 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[6])); - - mux_tree_tapbuf_size2 mux_top_track_14 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[7])); - - mux_tree_tapbuf_size2 mux_top_track_16 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[8])); - - mux_tree_tapbuf_size2 mux_top_track_18 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_top_out[9])); - - mux_tree_tapbuf_size2 mux_top_track_20 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_top_out[10])); - - mux_tree_tapbuf_size2 mux_top_track_22 ( - .in({top_left_grid_pin_41_[0], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_top_out[11])); - - mux_tree_tapbuf_size2 mux_top_track_26 ( - .in({top_left_grid_pin_35_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_top_out[13])); - - mux_tree_tapbuf_size2 mux_top_track_28 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chany_top_out[14])); - - mux_tree_tapbuf_size2 mux_top_track_30 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chany_top_out[15])); - - mux_tree_tapbuf_size2 mux_top_track_32 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chany_top_out[16])); - - mux_tree_tapbuf_size2 mux_top_track_34 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chany_top_out[17])); - - mux_tree_tapbuf_size2 mux_top_track_36 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), - .out(chany_top_out[18])); - - mux_tree_tapbuf_size2 mux_top_track_38 ( - .in({top_left_grid_pin_41_[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), - .out(chany_top_out[19])); - - mux_tree_tapbuf_size2 mux_left_track_11 ( - .in({chany_top_in[15], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), - .out(chanx_left_out[5])); - - mux_tree_tapbuf_size2 mux_left_track_13 ( - .in({chany_top_in[14], left_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), - .out(chanx_left_out[6])); - - mux_tree_tapbuf_size2 mux_left_track_15 ( - .in({chany_top_in[13], left_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), - .out(chanx_left_out[7])); - - mux_tree_tapbuf_size2 mux_left_track_17 ( - .in({chany_top_in[12], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size2 mux_left_track_19 ( - .in({chany_top_in[11], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), - .out(chanx_left_out[9])); - - mux_tree_tapbuf_size2 mux_left_track_21 ( - .in({chany_top_in[10], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), - .out(chanx_left_out[10])); - - mux_tree_tapbuf_size2 mux_left_track_23 ( - .in({chany_top_in[9], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size2_20_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), - .out(chanx_left_out[11])); - - mux_tree_tapbuf_size2 mux_left_track_27 ( - .in({chany_top_in[7], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_21_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), - .out(chanx_left_out[13])); - - mux_tree_tapbuf_size2_mem mem_top_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_28 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_30 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_34 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_36 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_38 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1])); + + +module sb_2__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:0] top_right_grid_pin_1_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_1_, + input [0:0] left_bottom_grid_pin_3_, + input [0:0] left_bottom_grid_pin_5_, + input [0:0] left_bottom_grid_pin_7_, + input [0:0] left_bottom_grid_pin_9_, + input [0:0] left_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_18_sram; + wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_19_sram; + wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + assign chanx_left_out[19] = chany_top_in[1]; + assign chanx_left_out[18] = chany_top_in[2]; + assign chanx_left_out[11] = chany_top_in[9]; + assign chanx_left_out[10] = chany_top_in[10]; + assign chany_top_out[19] = chanx_left_in[1]; + assign chany_top_out[18] = chanx_left_in[2]; + assign chany_top_out[17] = chanx_left_in[3]; + assign chany_top_out[16] = chanx_left_in[4]; + assign chany_top_out[15] = chanx_left_in[5]; + assign chany_top_out[14] = chanx_left_in[6]; + + mux_tree_tapbuf_size6 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0]) + ); + + + mux_tree_tapbuf_size6 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); + + + mux_tree_tapbuf_size5 + mux_top_track_6 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[3]) + ); + + + mux_tree_tapbuf_size5_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5_mem + mem_top_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[4]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_24 + ( + .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_10 + ( + .in({ top_left_grid_pin_43_[0], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_12 + ( + .in({ top_left_grid_pin_44_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_14 + ( + .in({ top_left_grid_pin_45_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_16 + ( + .in({ top_left_grid_pin_46_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_18 + ( + .in({ top_left_grid_pin_47_[0], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_top_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_20 + ( + .in({ top_left_grid_pin_48_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_top_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_22 + ( + .in({ top_left_grid_pin_49_[0], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_top_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_26 + ( + .in({ top_left_grid_pin_43_[0], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_top_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_9 + ( + .in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_11 + ( + .in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_13 + ( + .in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_15 + ( + .in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_17 + ( + .in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_19 + ( + .in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_25 + ( + .in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_27 + ( + .in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_1 + ( + .in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_3 + ( + .in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_5 + ( + .in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_7 + ( + .in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v index bc9f272..8aa2dd2 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v @@ -1,698 +1,862 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__1_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - top_right_grid_pin_1_, - chany_bottom_in, - bottom_right_grid_pin_1_, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - ccff_head, - chany_top_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:0] top_right_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_right_grid_pin_1_; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_2__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:0] top_right_grid_pin_1_, + input [0:19] chany_bottom_in, + input [0:0] bottom_right_grid_pin_1_, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:3] mux_tree_tapbuf_size14_0_sram; + wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size14_1_sram; + wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:3] mux_tree_tapbuf_size9_0_sram; + wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + assign chanx_left_out[13] = left_bottom_grid_pin_35_[0]; + + mux_tree_tapbuf_size10 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:3] mux_tree_tapbuf_size14_0_sram; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size14_1_sram; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_4_sram; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_5_sram; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_6_sram; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:3] mux_tree_tapbuf_size9_0_sram; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + mux_tree_tapbuf_size10 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_bottom_out[0]) + ); -// -// -// -// - assign chanx_left_out[19] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chanx_left_out[18] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chanx_left_out[17] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chanx_left_out[16] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chanx_left_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_left_out[14] = chany_top_in[19]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - assign chanx_left_out[13] = left_top_grid_pin_43_[0]; -// -// -// - mux_tree_tapbuf_size10 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size10_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(chany_bottom_out[0])); - mux_tree_tapbuf_size10_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(chany_top_out[1])); + mux_tree_tapbuf_size8 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[1]) + ); - mux_tree_tapbuf_size8 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(chany_top_out[4])); - mux_tree_tapbuf_size8 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size8 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size8_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); - mux_tree_tapbuf_size14 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), - .out(chany_top_out[2])); + mux_tree_tapbuf_size8_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size14 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size14_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); + mux_tree_tapbuf_size8_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); - mux_tree_tapbuf_size7 mux_top_track_16 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[8])); + mux_tree_tapbuf_size8_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7 mux_top_track_24 ( - .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_top_out[12])); - mux_tree_tapbuf_size7 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[8])); + mux_tree_tapbuf_size14 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chany_top_out[2]) + ); - mux_tree_tapbuf_size7 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_left_out[0])); - mux_tree_tapbuf_size7 mux_left_track_3 ( - .in({chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), - .out(chanx_left_out[1])); + mux_tree_tapbuf_size14 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size7 mux_left_track_5 ( - .in({chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size7 mux_left_track_7 ( - .in({chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), - .out(chanx_left_out[3])); + mux_tree_tapbuf_size14_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + mux_tree_tapbuf_size14_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_top_track_16 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_top_track_24 + ( + .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); - mux_tree_tapbuf_size6 mux_top_track_32 ( - .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[16])); + mux_tree_tapbuf_size7 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[6], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size6 mux_bottom_track_33 ( - .in({chany_top_in[10], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size7 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_left_track_3 + ( + .in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size7 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); - mux_tree_tapbuf_size4 mux_left_track_9 ( - .in({chany_top_in[8], chany_bottom_in[7:8], left_top_grid_pin_42_[0]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chanx_left_out[4])); + mux_tree_tapbuf_size7 + mux_left_track_7 + ( + .in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); - mux_tree_tapbuf_size4 mux_left_track_11 ( - .in({chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chanx_left_out[5])); - mux_tree_tapbuf_size4 mux_left_track_13 ( - .in({chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chanx_left_out[6])); + mux_tree_tapbuf_size7_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4 mux_left_track_15 ( - .in({chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_left_out[7])); - mux_tree_tapbuf_size4_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + mux_tree_tapbuf_size7_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_left_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_left_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + mux_tree_tapbuf_size7_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_left_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_left_track_17 ( - .in({chany_top_in[13], chany_bottom_in[13], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_left_out[8])); + mux_tree_tapbuf_size7_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_left_track_19 ( - .in({chany_top_in[14], chany_bottom_in[14], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_left_out[9])); - mux_tree_tapbuf_size3 mux_left_track_21 ( - .in({chany_top_in[16], chany_bottom_in[16], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_left_out[10])); + mux_tree_tapbuf_size7_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_left_track_23 ( - .in({chany_top_in[17], chany_bottom_in[17], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_left_out[11])); - mux_tree_tapbuf_size3 mux_left_track_25 ( - .in({chany_top_in[18], chany_bottom_in[18], left_top_grid_pin_42_[0]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chanx_left_out[12])); + mux_tree_tapbuf_size7_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_left_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + mux_tree_tapbuf_size7_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_left_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + mux_tree_tapbuf_size6 + mux_top_track_32 + ( + .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[16]) + ); + + + mux_tree_tapbuf_size6 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size6 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size9 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chany_bottom_out[1]) + ); + + + mux_tree_tapbuf_size9_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_9 + ( + .in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_11 + ( + .in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_13 + ( + .in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_15 + ( + .in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_17 + ( + .in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_19 + ( + .in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_21 + ( + .in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_23 + ( + .in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_left_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_25 + ( + .in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_37 + ( + .in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_39 + ( + .in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_37 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_39 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v index da1d675..cf2fdd6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v @@ -1,528 +1,884 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__2_(prog_clk, - chany_bottom_in, - bottom_right_grid_pin_1_, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_1_, - ccff_head, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_right_grid_pin_1_; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_2__2_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:0] bottom_right_grid_pin_1_, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_top_grid_pin_1_, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_18_sram; + wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_19_sram; + wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_20_sram; + wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_21_sram; + wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_22_sram; + wire [0:1] mux_tree_tapbuf_size2_22_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_23_sram; + wire [0:1] mux_tree_tapbuf_size2_23_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_2_sram; + wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_3_sram; + wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_3_sram; + wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; + assign chany_bottom_out[19] = chanx_left_in[0]; + assign chany_bottom_out[15] = chanx_left_in[16]; + assign chany_bottom_out[16] = chanx_left_in[17]; + assign chany_bottom_out[17] = chanx_left_in[18]; + assign chany_bottom_out[18] = chanx_left_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size6 + mux_bottom_track_1 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_12_sram; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_13_sram; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_14_sram; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_15_sram; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_16_sram; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_17_sram; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + mux_tree_tapbuf_size6 + mux_bottom_track_5 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); -// -// -// -// - assign chanx_left_out[1] = chany_bottom_in[0]; -// -// -// - assign chanx_left_out[3] = chany_bottom_in[2]; -// -// -// - assign chanx_left_out[5] = chany_bottom_in[4]; -// -// -// - assign chanx_left_out[6] = chany_bottom_in[5]; -// -// -// - assign chanx_left_out[7] = chany_bottom_in[6]; -// -// -// - assign chanx_left_out[8] = chany_bottom_in[7]; -// -// -// - assign chanx_left_out[9] = chany_bottom_in[8]; -// -// -// - assign chanx_left_out[10] = chany_bottom_in[9]; -// -// -// - assign chanx_left_out[11] = chany_bottom_in[10]; -// -// -// - assign chanx_left_out[13] = chany_bottom_in[12]; -// -// -// - assign chanx_left_out[14] = chany_bottom_in[13]; -// -// -// - assign chanx_left_out[15] = chany_bottom_in[14]; -// -// -// - assign chanx_left_out[16] = chany_bottom_in[15]; -// -// -// - assign chanx_left_out[17] = chany_bottom_in[16]; -// -// -// - assign chanx_left_out[18] = chany_bottom_in[17]; -// -// -// - assign chanx_left_out[19] = chany_bottom_in[18]; -// -// -// - mux_tree_tapbuf_size6 mux_bottom_track_1 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size6 + mux_left_track_1 + ( + .in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + mux_tree_tapbuf_size6 + mux_left_track_5 + ( + .in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_bottom_track_3 ( - .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_bottom_track_7 ( - .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_bottom_out[3])); - mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size6_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_bottom_track_25 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + mux_tree_tapbuf_size6_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - mux_tree_tapbuf_size2 mux_bottom_track_11 ( - .in({bottom_left_grid_pin_34_[0], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_bottom_out[5])); + mux_tree_tapbuf_size5 + mux_bottom_track_3 + ( + .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_13 ( - .in({bottom_left_grid_pin_35_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_bottom_out[6])); - mux_tree_tapbuf_size2 mux_bottom_track_15 ( - .in({bottom_left_grid_pin_36_[0], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_bottom_out[7])); + mux_tree_tapbuf_size5 + mux_bottom_track_7 + ( + .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_bottom_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_17 ( - .in({bottom_left_grid_pin_37_[0], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size2 mux_bottom_track_19 ( - .in({bottom_left_grid_pin_38_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[9])); + mux_tree_tapbuf_size5 + mux_left_track_3 + ( + .in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_21 ( - .in({bottom_left_grid_pin_39_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[10])); - mux_tree_tapbuf_size2 mux_bottom_track_23 ( - .in({bottom_left_grid_pin_40_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[11])); + mux_tree_tapbuf_size5 + mux_left_track_7 + ( + .in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in({bottom_left_grid_pin_34_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_bottom_out[13])); - mux_tree_tapbuf_size2 mux_bottom_track_29 ( - .in({bottom_left_grid_pin_35_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chany_bottom_out[14])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_31 ( - .in({bottom_left_grid_pin_36_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chany_bottom_out[15])); - mux_tree_tapbuf_size2 mux_bottom_track_33 ( - .in({bottom_left_grid_pin_37_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_35 ( - .in({bottom_left_grid_pin_38_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chany_bottom_out[17])); - mux_tree_tapbuf_size2 mux_bottom_track_37 ( - .in({bottom_left_grid_pin_39_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), - .out(chany_bottom_out[18])); + mux_tree_tapbuf_size5_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in({bottom_left_grid_pin_40_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), - .out(chany_bottom_out[19])); - mux_tree_tapbuf_size2 mux_left_track_1 ( - .in({chany_bottom_in[19], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), - .out(chanx_left_out[0])); + mux_tree_tapbuf_size5_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_left_track_5 ( - .in({chany_bottom_in[1], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size2 mux_left_track_9 ( - .in({chany_bottom_in[3], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), - .out(chanx_left_out[4])); + mux_tree_tapbuf_size2 + mux_bottom_track_9 + ( + .in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size2 mux_left_track_25 ( - .in({chany_bottom_in[11], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), - .out(chanx_left_out[12])); - mux_tree_tapbuf_size2_mem mem_bottom_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_11 + ( + .in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[5]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_13 + ( + .in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[6]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_15 + ( + .in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[7]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_17 + ( + .in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_19 + ( + .in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[9]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_21 + ( + .in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[10]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_23 + ( + .in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_bottom_out[11]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_27 + ( + .in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chany_bottom_out[13]) + ); - mux_tree_tapbuf_size2_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_29 + ( + .in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chany_bottom_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_11 + ( + .in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_13 + ( + .in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_15 + ( + .in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_17 + ( + .in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_19 + ( + .in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_21 + ( + .in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_23 + ( + .in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_27 + ( + .in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_37 + ( + .in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_22_sram_inv[0:1]), + .out(chanx_left_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_39 + ( + .in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_23_sram_inv[0:1]), + .out(chanx_left_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_37 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_22_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_39 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_23_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_25 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_9 + ( + .in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_25 + ( + .in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v new file mode 100644 index 0000000..0dcc04f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v @@ -0,0 +1,63 @@ +`timescale 1ns/1ps + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule + + +// +// +// +// +module EMBEDDED_IO ( + input SOC_IN, // + output SOC_OUT, // + output SOC_DIR, // + output FPGA_IN, // + input FPGA_OUT, // + input FPGA_DIR // +); + + assign FPGA_IN = SOC_IN; + assign SOC_OUT = FPGA_OUT; + assign SOC_DIR = FPGA_DIR; +endmodule + +// +// +// +module GPIN ( + inout A, // + output Y // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule + +// +// +// +module GPOUT ( + inout Y, // + input A // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v index bbe4829..ad8b2cc 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v @@ -130,6 +130,226 @@ endmodule +// +module mux_tree_tapbuf_size4_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size11_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:1] mem_out; +// +output [0:1] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + // module mux_tree_tapbuf_size6_mem(prog_clk, ccff_head, @@ -240,281 +460,6 @@ endmodule -// -module mux_tree_tapbuf_size14_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; -// -output [0:3] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; -// -output [0:1] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; -// -output [0:1] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; -// -output [0:2] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; -// -output [0:3] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); - -endmodule -// - - - // module mux_tree_tapbuf_size12_mem(prog_clk, ccff_head, @@ -644,7 +589,7 @@ endmodule // -module mux_tree_tapbuf_size4_mem(prog_clk, +module mux_tree_tapbuf_size3_mem(prog_clk, ccff_head, ccff_tail, mem_out, @@ -656,9 +601,9 @@ input [0:0] ccff_head; // output [0:0] ccff_tail; // -output [0:2] mem_out; +output [0:1] mem_out; // -output [0:2] mem_outb; +output [0:1] mem_outb; // // @@ -672,7 +617,56 @@ output [0:2] mem_outb; // // // - assign ccff_tail[0] = mem_out[2]; + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; // sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( @@ -693,6 +687,73 @@ output [0:2] mem_outb; .Q(mem_out[2]), .Q_N(mem_outb[2])); + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + endmodule // @@ -887,11 +948,11 @@ endmodule // -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); // input [0:0] prog_clk; // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v index 7ddd317..9d0204a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v @@ -216,6 +216,338 @@ endmodule +// +module mux_tree_tapbuf_size4(in, + sram, + sram_inv, + out); +// +input [0:3] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_3_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7(in, + sram, + sram_inv, + out); +// +input [0:6] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_6_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size11(in, + sram, + sram_inv, + out); +// +input [0:10] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_10_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[10]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_8_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_9_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +// +input [0:1] in; +// +input [0:1] sram; +// +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_1_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + +endmodule +// + + + // module mux_tree_tapbuf_size6(in, sram, @@ -375,456 +707,6 @@ endmodule -// -module mux_tree_tapbuf_size14(in, - sram, - sram_inv, - out); -// -input [0:13] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_13_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( - .A1(in[10]), - .A0(in[11]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( - .A1(in[12]), - .A0(in[13]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_13_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3(in, - sram, - sram_inv, - out); -// -input [0:2] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_2_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2(in, - sram, - sram_inv, - out); -// -input [0:1] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_1_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7(in, - sram, - sram_inv, - out); -// -input [0:6] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_6_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9(in, - sram, - sram_inv, - out); -// -input [0:8] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_8_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[8]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - -endmodule -// - - - // module mux_tree_tapbuf_size12(in, sram, @@ -1104,16 +986,78 @@ endmodule // -module mux_tree_tapbuf_size4(in, +module mux_tree_tapbuf_size3(in, sram, sram_inv, out); // -input [0:3] in; +input [0:2] in; // -input [0:2] sram; +input [0:1] sram; // -input [0:2] sram_inv; +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_2_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9(in, + sram, + sram_inv, + out); +// +input [0:8] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; // output [0:0] out; @@ -1130,6 +1074,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; // // @@ -1140,7 +1089,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; .const1(const1_0_const1[0])); sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A(sky130_fd_sc_hd__mux2_1_8_X[0]), .X(out[0])); sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( @@ -1149,24 +1098,193 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; .S(sram[0]), .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(in[2]), - .S(sram[1]), + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[3]), - .A0(const1_0_const1[0]), + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), .S(sram[1]), .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), - .S(sram[2]), + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[1]), .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[8]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14(in, + sram, + sram_inv, + out); +// +input [0:13] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_13_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_13_X[0])); + endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v index d288329..b710461 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v @@ -15,12 +15,11 @@ wire [0:0] Test_en; wire [0:0] clk; // -wire [0:7] gfpga_pad_GPIO_Y; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; -wire [0:7] gfpga_pad_GPIO_A; -wire [0:7] gfpga_pad_GPIO_IE; -wire [0:7] gfpga_pad_GPIO_OE; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; reg [0:0] config_done; wire [0:0] prog_clock; @@ -85,7 +84,7 @@ initial end always wait(~greset) begin - #0.4159859717 op_clock_reg[0] = ~op_clock_reg[0]; + #0.5203860402 op_clock_reg[0] = ~op_clock_reg[0]; end // @@ -116,8 +115,8 @@ initial begin greset[0] = 1'b1; wait(config_done) - #0.8319719434 greset[0] = 1'b1; - #1.663943887 greset[0] = 1'b0; + #1.04077208 greset[0] = 1'b1; + #2.081544161 greset[0] = 1'b0; end // @@ -139,27 +138,57 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0])); // // - assign gfpga_pad_GPIO_Y[4] = a[0]; -// - assign gfpga_pad_GPIO_Y[6] = b[0]; -// - assign out:c_fpga[0] = gfpga_pad_GPIO_Y[5]; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a[0]; // - assign gfpga_pad_GPIO_Y[0] = 1'b0; - assign gfpga_pad_GPIO_Y[1] = 1'b0; - assign gfpga_pad_GPIO_Y[2] = 1'b0; - assign gfpga_pad_GPIO_Y[3] = 1'b0; - assign gfpga_pad_GPIO_Y[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b[0]; + +// + assign out:c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; + +// + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; `ifdef AUTOCHECKED_SIMULATION // @@ -206,17 +235,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -231,9 +253,8 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -245,6 +266,7 @@ initial prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); @@ -319,80 +341,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); @@ -419,30 +367,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -808,22 +741,18 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -884,10 +813,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1086,6 +1015,47 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1188,6 +1158,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1240,32 +1211,8 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2016,10 +1963,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2045,6 +1988,38 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2138,6 +2113,67 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2195,6 +2231,96 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); @(negedge prog_clock[0]); config_done[0] <= 1'b1; end @@ -2260,7 +2386,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // - #20121 + #21092 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v index 0a9714c..745bf34 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v @@ -53,7 +53,7 @@ module top_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4159859701 + #0.5203860242 clk[0] <= !clk[0]; end end @@ -112,7 +112,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // - #332 + #416 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v index a68418f..e4ba114 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v @@ -17,10 +17,9 @@ output [0:0] out:c_fm); wire [0:0] prog_clk; wire [0:0] Test_en; wire [0:0] clk; -wire [0:7] gfpga_pad_GPIO_Y; -wire [0:7] gfpga_pad_GPIO_A; -wire [0:7] gfpga_pad_GPIO_IE; -wire [0:7] gfpga_pad_GPIO_OE; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; wire [0:0] ccff_head; wire [0:0] ccff_tail; @@ -29,10 +28,9 @@ wire [0:0] ccff_tail; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0])); @@ -43,18 +41,49 @@ wire [0:0] ccff_tail; // // - assign gfpga_pad_GPIO_Y[4] = a_fm[0]; -// - assign gfpga_pad_GPIO_Y[6] = b_fm[0]; -// - assign out:c_fm[0] = gfpga_pad_GPIO_Y[5]; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a_fm[0]; // - assign gfpga_pad_GPIO_Y[0] = 1'b0; - assign gfpga_pad_GPIO_Y[1] = 1'b0; - assign gfpga_pad_GPIO_Y[2] = 1'b0; - assign gfpga_pad_GPIO_Y[3] = 1'b0; - assign gfpga_pad_GPIO_Y[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b_fm[0]; + +// + assign out:c_fm[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; + +// + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; // `ifdef ICARUS_SIMULATOR @@ -94,7 +123,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000110000001; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000100010001; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; @@ -219,32 +248,44 @@ wire [0:0] ccff_tail; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; - assign U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; assign U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b010; - assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b1}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = 3'b110; + assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b001; + assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; @@ -253,7 +294,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = 3'b100; assign U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; @@ -266,22 +307,43 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = 3'b010; + assign U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = 3'b110; assign U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = 4'b0010; assign U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; @@ -291,26 +353,21 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3] = 4'b0010; + assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; @@ -328,7 +385,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = 4'b0110; assign U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4] = {5{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; @@ -341,14 +398,14 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = 3'b001; + assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; @@ -363,16 +420,10 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; @@ -390,12 +441,6 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; @@ -406,10 +451,12 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3] = {4{1'b0}}; @@ -437,6 +484,12 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; @@ -452,88 +505,106 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3] = 4'b1101; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; @@ -546,11 +617,10 @@ wire [0:0] ccff_tail; assign U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b1}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = 4'b0111; assign U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; @@ -637,7 +707,7 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111001111110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111011101110; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = 2'b10; @@ -762,32 +832,44 @@ initial begin force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; - force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b101; - force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = 3'b001; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b110; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; @@ -796,7 +878,7 @@ initial begin force U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = 3'b011; force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; @@ -809,22 +891,43 @@ initial begin force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = 3'b101; + force U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = 3'b001; force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = 4'b1101; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; @@ -834,26 +937,21 @@ initial begin force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3] = 4'b1101; + force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; @@ -871,7 +969,7 @@ initial begin force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = 4'b1001; force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4] = {5{1'b1}}; force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; @@ -884,14 +982,14 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = 3'b110; + force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -906,16 +1004,10 @@ initial begin force U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; @@ -933,12 +1025,6 @@ initial begin force U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -949,10 +1035,12 @@ initial begin force U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3] = {4{1'b1}}; @@ -980,6 +1068,12 @@ initial begin force U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -995,88 +1089,106 @@ initial begin force U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3] = 4'b0010; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; @@ -1089,11 +1201,10 @@ initial begin force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = 4'b1000; force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; @@ -1219,8 +1330,8 @@ initial begin $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], 17'b00000000110000001); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], 17'b11111111001111110); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], 17'b00000000100010001); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], 17'b11111111011101110); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); @@ -1469,42 +1580,62 @@ initial begin $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b010); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b101); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], 3'b110); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], 3'b001); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b001); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b110); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); @@ -1513,14 +1644,18 @@ initial begin $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); @@ -1537,8 +1672,8 @@ initial begin $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], 3'b100); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], 3'b011); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); @@ -1563,28 +1698,70 @@ initial begin $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], 3'b010); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], 3'b101); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], 3'b110); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], 3'b001); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1], {2{1'b0}}); @@ -1593,8 +1770,8 @@ initial begin $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], 4'b0010); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], 4'b1101); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); @@ -1613,32 +1790,22 @@ initial begin $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3], 4'b0010); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3], 4'b1101); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); @@ -1647,12 +1814,12 @@ initial begin $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); @@ -1687,8 +1854,8 @@ initial begin $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], 4'b0110); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], 4'b1001); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4], {5{1'b0}}); @@ -1713,22 +1880,22 @@ initial begin $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], 3'b001); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], 3'b110); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); @@ -1757,26 +1924,14 @@ initial begin $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); @@ -1811,18 +1966,6 @@ initial begin $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); @@ -1843,14 +1986,18 @@ initial begin $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); @@ -1905,6 +2052,18 @@ initial begin $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); @@ -1935,170 +2094,206 @@ initial begin $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3], 4'b1101); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3], 4'b0010); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); @@ -2123,16 +2318,14 @@ initial begin $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], 4'b0111); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], 4'b1000); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit index 546bf36..3763705 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit @@ -1 +1 @@ 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9188,9 +9423,9 @@ - + - + @@ -9209,13 +9444,261 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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- - - - - - - - - - - - - - - - - - - - - - - - - @@ -10114,7 +10489,7 @@ - + @@ -10126,22 +10501,162 @@ - + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + @@ -10165,11 +10680,63 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -10193,63 +10760,11 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -10273,11 +10788,63 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -10301,63 +10868,11 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -10381,11 +10896,63 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -10409,63 +10976,11 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -10489,11 +11004,63 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -10517,58 +11084,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -10599,17 +11114,15 @@ - - - + - - + + - + @@ -10629,6 +11142,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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-11088,13 +11951,13 @@ - + - - - - - + + + + + @@ -11112,8 +11975,6 @@ - - @@ -11132,23 +11993,23 @@ - - + + - + - + - + - - - + + + @@ -11166,6 +12027,8 @@ + + @@ -11179,34 +12042,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -11250,8 +12085,6 @@ - - @@ -11304,6 +12137,8 @@ + + @@ -11358,8 +12193,6 @@ - - @@ -11410,8 +12243,10 @@ - + + + @@ -11466,8 +12301,6 @@ - - @@ -11518,8 +12351,10 @@ - + + + @@ -11574,8 +12409,6 @@ - - @@ -11628,6 +12461,8 @@ + + @@ -11712,8 +12547,6 @@ - - @@ -11766,6 +12599,8 @@ + + @@ -11820,8 +12655,6 @@ - - @@ -11874,6 +12707,8 @@ + + @@ -11928,8 +12763,6 @@ - - @@ -11982,6 +12815,8 @@ + + @@ -12036,8 +12871,6 @@ - - @@ -12090,6 +12923,8 @@ + + @@ -12174,8 +13009,6 @@ - - @@ -12228,6 +13061,8 @@ + + @@ -12282,8 +13117,6 @@ - - @@ -12336,6 +13169,8 @@ + + @@ -12390,8 +13225,6 @@ - - @@ -12444,6 +13277,8 @@ + + @@ -12498,8 +13333,6 @@ - - @@ -12552,6 +13385,8 @@ + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log index 365b894..8da0c6f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log @@ -41,9 +41,9 @@ THE SOFTWARE. Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off VPR FPGA Placement and Routing. -Version: 0.0.0+48b2bff0 -Revision: 48b2bff0 -Compiled: 2020-09-27T20:43:27 +Version: 0.0.0+55f7a2c1 +Revision: 55f7a2c1 +Compiled: 2020-11-05T12:41:40 Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 Build Info: release VTR_ASSERT_LEVEL=2 @@ -65,35 +65,27 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -# Loading Architecture Description took 0.00 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB) +# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB) # Building complex block graph -Warning 6: [LINE 546] false logically-equivalent pin clb[0].I0[1]. -Warning 7: [LINE 546] false logically-equivalent pin clb[0].I0[2]. -Warning 8: [LINE 546] false logically-equivalent pin clb[0].I0[3]. -Warning 9: [LINE 548] false logically-equivalent pin clb[0].I1[1]. -Warning 10: [LINE 548] false logically-equivalent pin clb[0].I1[2]. -Warning 11: [LINE 548] false logically-equivalent pin clb[0].I1[3]. -Warning 12: [LINE 550] false logically-equivalent pin clb[0].I2[1]. -Warning 13: [LINE 550] false logically-equivalent pin clb[0].I2[2]. -Warning 14: [LINE 550] false logically-equivalent pin clb[0].I2[3]. -Warning 15: [LINE 552] false logically-equivalent pin clb[0].I3[1]. -Warning 16: [LINE 552] false logically-equivalent pin clb[0].I3[2]. -Warning 17: [LINE 552] false logically-equivalent pin clb[0].I3[3]. -Warning 18: [LINE 554] false logically-equivalent pin clb[0].I4[1]. -Warning 19: [LINE 554] false logically-equivalent pin clb[0].I4[2]. -Warning 20: [LINE 554] false logically-equivalent pin clb[0].I4[3]. -Warning 21: [LINE 556] false logically-equivalent pin clb[0].I5[1]. -Warning 22: [LINE 556] false logically-equivalent pin clb[0].I5[2]. -Warning 23: [LINE 556] false logically-equivalent pin clb[0].I5[3]. -Warning 24: [LINE 558] false logically-equivalent pin clb[0].I6[1]. -Warning 25: [LINE 558] false logically-equivalent pin clb[0].I6[2]. -Warning 26: [LINE 558] false logically-equivalent pin clb[0].I6[3]. -Warning 27: [LINE 560] false logically-equivalent pin clb[0].I7[1]. -Warning 28: [LINE 560] false logically-equivalent pin clb[0].I7[2]. -Warning 29: [LINE 560] false logically-equivalent pin clb[0].I7[3]. -# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.8 MiB) +Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1]. +Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2]. +Warning 8: [LINE 588] false logically-equivalent pin clb[0].I1[1]. +Warning 9: [LINE 588] false logically-equivalent pin clb[0].I1[2]. +Warning 10: [LINE 594] false logically-equivalent pin clb[0].I2[1]. +Warning 11: [LINE 594] false logically-equivalent pin clb[0].I2[2]. +Warning 12: [LINE 600] false logically-equivalent pin clb[0].I3[1]. +Warning 13: [LINE 600] false logically-equivalent pin clb[0].I3[2]. +Warning 14: [LINE 606] false logically-equivalent pin clb[0].I4[1]. +Warning 15: [LINE 606] false logically-equivalent pin clb[0].I4[2]. +Warning 16: [LINE 612] false logically-equivalent pin clb[0].I5[1]. +Warning 17: [LINE 612] false logically-equivalent pin clb[0].I5[2]. +Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1]. +Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2]. +Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1]. +Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2]. +# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) # Load circuit -# Load circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.3 MiB) +# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) # Clean circuit Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 0 additional primitive pins as constant generators due to constant inputs @@ -102,11 +94,11 @@ Swept output(s) : 0 (0 dangling, 0 constant) Swept net(s) : 0 Swept block(s) : 0 Constant Pins Marked: 0 -# Clean circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) # Compress circuit -# Compress circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) # Verify circuit -# Verify circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Circuit Statistics: Blocks: 4 .input : 2 @@ -121,7 +113,7 @@ Circuit Statistics: Timing Graph Nodes: 6 Timing Graph Edges: 5 Timing Graph Levels: 4 -# Build Timing Graph took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Netlist contains 0 clocks # Load Timing Constraints @@ -132,7 +124,7 @@ Setting default timing constraints: Timing constraints created 1 clocks Constrained Clock 'virtual_io_clock' (Virtual Clock) -# Load Timing Constraints took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Timing analysis: ON Circuit netlist file: top.net Circuit placement file: top.place @@ -201,6 +193,10 @@ RoutingArch.switch_block_type: WILTON RoutingArch.Fs: 3 # Packing +Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 23: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 24: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 25: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Begin packing 'top.blif'. After removing unused inputs... @@ -208,8 +204,12 @@ After removing unused inputs... Begin prepacking. Finish prepacking. Using inter-cluster delay: 1.33777e-09 -Packing with pin utilization targets: io:1,1 clb:0.8,1 -Packing with high fanout thresholds: io:128 clb:32 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 +Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 27: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 28: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 29: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Not enough resources expand FPGA size to (4 x 4) Complex block 0: 'c' (clb) . Complex block 1: 'out:c' (io) . @@ -238,23 +238,27 @@ Logic Element (fle) detailed count: io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. +Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 31: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 32: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 33: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 4 x 4 (2x2) Device Utilization: 0.25 (target 1.00) - Block Utilization: 0.38 Type: io + Block Utilization: 0.17 Type: io Block Utilization: 0.25 Type: clb Netlist conversion complete. -# Packing took 0.01 seconds (max_rss 10.5 MiB, delta_rss +0.7 MiB) +# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0.02 seconds). -Warning 30: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). +Finished loading packed FPGA netlist file (took 0.01 seconds). +Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) -Warning 31: Netlist contains 0 global net to non-global architecture pin connections +Warning 35: Netlist contains 0 global net to non-global architecture pin connections Netlist num_nets: 3 Netlist num_blocks: 4 @@ -266,237 +270,219 @@ Netlist output pins: 1 # Create Device ## Build Device Grid +Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 37: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 38: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 39: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 4 x 4: 16 grid tiles (2x2) Resource usage... Netlist 3 blocks of type: io Architecture - 8 blocks of type: io + 2 blocks of type: io_top + 2 blocks of type: io_right + 12 blocks of type: io_bottom + 2 blocks of type: io_left Netlist 1 blocks of type: clb Architecture 4 blocks of type: clb Device Utilization: 0.25 (target 1.00) - Physical Tile io: - Block Utilization: 0.38 Logical Block: io + Physical Tile io_top: + Block Utilization: 1.50 Logical Block: io + Physical Tile io_right: + Block Utilization: 1.50 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.25 Logical Block: io + Physical Tile io_left: + Block Utilization: 1.50 Logical Block: io Physical Tile clb: Block Utilization: 0.25 Logical Block: clb -## Build Device Grid took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.0 MiB) +## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB) ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 -Warning 32: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 33: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 34: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 35: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 36: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) - RR Graph Nodes: 684 - RR Graph Edges: 2780 -# Create Device took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) +Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2930 +# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) # Placement ## Computing placement delta delay look-up ### Build routing resource graph -Warning 37: in check_rr_node: RR node: 109 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 38: in check_rr_node: RR node: 110 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 39: in check_rr_node: RR node: 293 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 40: in check_rr_node: RR node: 294 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 41: in check_rr_graph: fringe node 2 IPIN at (0,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -### Build routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 732 - RR Graph Edges: 2188 +Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2428 ### Computing delta delays -### Computing delta delays took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) -## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) +### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB) +## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB) There are 3 point to point connections in this circuit. -BB estimate of min-dist (placement) wire length: 11 +BB estimate of min-dist (placement) wire length: 10 Completed placement consistency check successfully. -Initial placement cost: 1 bb_cost: 0.275 td_cost: 5.6541e-10 -Initial placement estimated Critical Path Delay (CPD): 0.69331 ns -Initial placement estimated setup Total Negative Slack (sTNS): -0.69331 ns -Initial placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns +Initial placement cost: 1 bb_cost: 0.25 td_cost: 6.04709e-10 +Initial placement estimated Critical Path Delay (CPD): 0.80931 ns +Initial placement estimated setup Total Negative Slack (sTNS): -0.80931 ns +Initial placement estimated setup Worst Negative Slack (sWNS): -0.80931 ns Initial placement estimated setup slack histogram: -[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 1 (100.0%) |************************************************** +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | Placement contains 0 placement macros involving 0 blocks (average macro size -nan) ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ -5.6e-01 0.892 0.21 5.1708e-10 0.693 -0.693 -0.693 1.000 0.0754 3.0 1.00 6 0.500 -2.8e-01 1.001 0.25 5.8474e-10 0.693 -0.693 -0.693 1.000 0.1044 3.0 1.00 12 0.500 -1.4e-01 0.828 0.19 5.1901e-10 0.751 -0.751 -0.751 0.833 0.0971 3.0 1.00 18 0.900 -1.3e-01 1.119 0.21 5.3388e-10 0.693 -0.693 -0.693 0.500 0.0412 3.0 1.00 24 0.950 -1.2e-01 1.017 0.24 5.3998e-10 0.693 -0.693 -0.693 0.833 0.0366 3.0 1.00 30 0.900 -1.1e-01 0.960 0.24 5.3641e-10 0.693 -0.693 -0.693 1.000 0.0433 3.0 1.00 36 0.500 -5.4e-02 0.970 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0405 3.0 1.00 42 0.950 -5.1e-02 0.974 0.19 4.4803e-10 0.635 -0.635 -0.635 0.667 0.0470 3.0 1.00 48 0.950 -4.9e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 54 0.950 -4.6e-02 1.063 0.19 4.5701e-10 0.635 -0.635 -0.635 0.500 0.0549 2.7 2.12 60 0.950 -4.4e-02 1.019 0.21 4.9794e-10 0.693 -0.693 -0.693 0.667 0.0458 2.8 1.56 66 0.950 -4.2e-02 1.043 0.21 5.1943e-10 0.693 -0.693 -0.693 0.667 0.0215 3.0 1.00 72 0.950 -4.0e-02 0.903 0.18 4.7533e-10 0.751 -0.751 -0.751 0.500 0.0052 3.0 1.00 78 0.950 -3.8e-02 1.042 0.20 4.4941e-10 0.693 -0.693 -0.693 0.333 0.0000 3.0 1.00 84 0.950 -3.6e-02 1.000 0.20 4.2544e-10 0.635 -0.635 -0.635 0.167 0.0000 2.7 2.12 90 0.950 -3.4e-02 1.069 0.22 4.4576e-10 0.635 -0.635 -0.635 0.667 0.0458 1.9 4.68 96 0.950 -3.2e-02 0.969 0.21 4.6916e-10 0.693 -0.693 -0.693 0.667 0.0361 2.4 3.14 102 0.950 -3.1e-02 0.968 0.19 4.7066e-10 0.693 -0.693 -0.693 0.500 0.0537 2.9 1.24 108 0.950 -2.9e-02 0.997 0.18 4.322e-10 0.635 -0.635 -0.635 0.500 0.0000 3.0 1.00 114 0.950 -2.8e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 120 0.950 -2.6e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 2.7 2.12 126 0.950 -2.5e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 2.8 1.56 132 0.950 -2.4e-02 0.994 0.18 4.0763e-10 0.635 -0.635 -0.635 0.167 0.0000 2.5 2.62 138 0.950 -2.3e-02 0.996 0.18 3.9202e-10 0.635 -0.635 -0.635 0.500 0.0064 1.8 5.05 144 0.950 -2.1e-02 1.000 0.18 4.0247e-10 0.635 -0.635 -0.635 0.333 0.0000 2.0 4.66 150 0.950 -2.0e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.7 5.39 156 0.950 -1.9e-02 1.071 0.20 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 7.06 162 0.950 -1.8e-02 0.967 0.18 5.0741e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.79 168 0.950 -1.7e-02 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 174 0.950 -1.7e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 180 0.950 -1.6e-02 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 186 0.950 -1.5e-02 0.989 0.18 3.5797e-10 0.635 -0.635 -0.635 0.667 0.0076 1.1 7.79 192 0.950 -1.4e-02 1.000 0.18 3.8602e-10 0.635 -0.635 -0.635 0.667 0.0000 1.3 6.95 198 0.950 -1.3e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.6 5.92 204 0.950 -1.3e-02 0.991 0.18 3.7094e-10 0.635 -0.635 -0.635 0.500 0.0078 1.4 6.51 210 0.950 -1.2e-02 0.995 0.18 3.809e-10 0.635 -0.635 -0.635 0.333 0.0113 1.5 6.21 216 0.950 -1.2e-02 1.000 0.18 4.1466e-10 0.693 -0.693 -0.693 0.167 0.0000 1.3 6.78 222 0.950 -1.1e-02 0.971 0.18 3.491e-10 0.693 -0.693 -0.693 0.500 0.0000 1.0 8.00 228 0.950 -1.0e-02 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 234 0.950 -9.9e-03 1.015 0.18 4.086e-10 0.635 -0.635 -0.635 0.333 0.0205 1.0 8.00 240 0.950 -9.4e-03 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 246 0.950 -9.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.667 0.0000 1.0 8.00 252 0.950 -8.5e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.333 0.0000 1.2 7.21 258 0.950 -8.1e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.66 264 0.950 -7.7e-03 1.000 0.18 3.8297e-10 0.635 -0.635 -0.635 0.167 0.0000 1.2 7.43 270 0.950 -7.3e-03 0.992 0.18 3.6408e-10 0.635 -0.635 -0.635 0.667 0.0090 1.0 8.00 276 0.950 -6.9e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.500 0.0000 1.2 7.21 282 0.950 -6.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 6.95 288 0.950 -6.3e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.4 6.68 294 0.950 -5.9e-03 1.000 0.18 3.8973e-10 0.635 -0.635 -0.635 0.500 0.0000 1.5 6.39 300 0.950 -5.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.5 6.08 306 0.950 -5.4e-03 0.995 0.18 3.788e-10 0.635 -0.635 -0.635 0.500 0.0079 1.4 6.66 312 0.950 -5.1e-03 1.000 0.18 3.8986e-10 0.635 -0.635 -0.635 0.167 0.0000 1.5 6.37 318 0.950 -4.8e-03 1.000 0.18 3.8095e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.77 324 0.950 -4.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.55 330 0.950 -4.4e-03 0.995 0.18 3.7402e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.31 336 0.950 -4.1e-03 0.986 0.18 3.5684e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 7.06 342 0.950 -3.9e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 348 0.950 -3.7e-03 0.985 0.18 3.5034e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 354 0.950 -3.6e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 360 0.950 -3.4e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 366 0.950 -3.2e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.79 372 0.950 -3.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.57 378 0.950 -2.9e-03 0.995 0.18 3.7386e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.33 384 0.950 -2.8e-03 0.990 0.18 3.6614e-10 0.635 -0.635 -0.635 0.500 0.0082 1.3 7.08 390 0.950 -2.6e-03 1.000 0.18 3.8688e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.82 396 0.950 -2.5e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 402 0.950 -2.4e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.000 0.0000 1.1 7.79 408 0.950 -2.2e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 414 0.950 -2.1e-03 0.995 0.18 3.7067e-10 0.635 -0.635 -0.635 0.500 0.0088 1.1 7.79 420 0.950 -2.0e-03 0.985 0.18 3.5227e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.57 426 0.950 -1.9e-03 0.992 0.18 3.6418e-10 0.635 -0.635 -0.635 0.333 0.0110 1.0 7.99 432 0.950 -1.8e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 438 0.950 -1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 444 0.950 -1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 450 0.000 +9.2e-01 0.857 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0425 3.0 1.00 6 0.950 +8.8e-01 1.031 0.22 5.2788e-10 0.693 -0.693 -0.693 1.000 0.1248 3.0 1.00 12 0.500 +4.4e-01 0.977 0.20 4.5978e-10 0.693 -0.693 -0.693 1.000 0.0478 3.0 1.00 18 0.500 +2.2e-01 1.296 0.24 6.1181e-10 0.577 -0.577 -0.577 0.833 0.1114 3.0 1.00 24 0.900 +2.0e-01 0.807 0.21 5.1793e-10 0.809 -0.809 -0.809 0.833 0.1585 3.0 1.00 30 0.900 +1.8e-01 1.284 0.23 4.5908e-10 0.577 -0.577 -0.577 1.000 0.1344 3.0 1.00 36 0.500 +8.9e-02 0.981 0.23 4.8318e-10 0.635 -0.635 -0.635 1.000 0.0703 3.0 1.00 42 0.500 +4.4e-02 0.906 0.23 4.617e-10 0.693 -0.693 -0.693 0.833 0.0159 3.0 1.00 48 0.900 +4.0e-02 0.915 0.20 4.3008e-10 0.693 -0.693 -0.693 1.000 0.0692 3.0 1.00 54 0.500 +2.0e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 3.0 1.00 60 0.950 +1.9e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.7 2.12 66 0.950 +1.8e-02 0.982 0.17 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0357 1.9 4.68 72 0.950 +1.7e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.4 3.14 78 0.950 +1.6e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.7 5.42 84 0.950 +1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 7.08 90 0.950 +1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 6.82 96 0.950 +1.4e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.4 6.54 102 0.950 +1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.3 7.07 108 0.950 +1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.54 114 0.950 +1.2e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.2 7.30 120 0.950 +1.1e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 126 0.800 +9.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 132 0.950 +8.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 138 0.950 +8.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 144 0.950 +7.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.99 150 0.950 +7.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 156 0.950 +7.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0000 1.1 7.79 162 0.950 +6.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.833 0.0000 1.3 6.95 168 0.900 +6.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.8 5.16 174 0.950 +5.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.95 180 0.950 +5.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 8.00 186 0.950 +5.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 192 0.950 +4.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.1 7.79 198 0.950 +4.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 204 0.950 +4.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 210 0.950 +4.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 216 0.950 +4.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 222 0.950 +3.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 7.99 228 0.950 +3.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 234 0.950 +3.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 240 0.950 +3.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 246 0.950 +3.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.79 252 0.950 +2.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 258 0.800 +2.3e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 264 0.950 +2.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 270 0.950 +2.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 276 0.800 +1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 282 0.950 +1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 288 0.000 -BB estimate of min-dist (placement) wire length: 7 +BB estimate of min-dist (placement) wire length: 6 Completed placement consistency check successfully. -Swaps called: 454 +Swaps called: 292 -Placement estimated critical path delay: 0.63531 ns -Placement estimated setup Total Negative Slack (sTNS): -0.63531 ns -Placement estimated setup Worst Negative Slack (sWNS): -0.63531 ns +Placement estimated critical path delay: 0.57731 ns +Placement estimated setup Total Negative Slack (sTNS): -0.57731 ns +Placement estimated setup Worst Negative Slack (sWNS): -0.57731 ns Placement estimated setup slack histogram: -[ -6.4e-10: -6.4e-10) 1 (100.0%) |************************************************** -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 1 (100.0%) |************************************************** +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -Placement cost: 1, bb_cost: 0.175, td_cost: 4.4941e-10, +Placement cost: 1, bb_cost: 0.15, td_cost: 3.9141e-10, Placement resource usage: - io implemented as io : 3 - clb implemented as clb: 1 + io implemented as io_bottom: 2 + io implemented as io_left : 1 + clb implemented as clb : 1 -Placement number of temperatures: 75 -Placement total # of swap attempts: 454 - Swaps accepted: 208 (45.8 %) - Swaps rejected: 246 (54.2 %) +Placement number of temperatures: 48 +Placement total # of swap attempts: 292 + Swaps accepted: 125 (42.8 %) + Swaps rejected: 167 (57.2 %) Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.5 MiB) +# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB) # Routing ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 -Warning 42: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 43: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 44: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 45: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 46: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.00 seconds (max_rss 11.6 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 684 - RR Graph Edges: 2780 +Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2930 Confirming router algorithm: TIMING_DRIVEN. ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- - 1 0.0 0.0 0 80 3 3 0 ( 0.000%) 6 ( 1.2%) 0.693 -0.6933 -0.693 0.000 0.000 N/A + 1 0.0 0.0 0 203 3 3 1 ( 0.132%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A + 2 0.0 0.5 0 86 1 1 0 ( 0.000%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A Restoring best routing -Critical path: 0.69331 ns -Successfully routed after 1 routing iterations. -Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 80 total_heap_pops: 45 -# Routing took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.1 MiB) +Critical path: 0.86731 ns +Successfully routed after 2 routing iterations. +Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187 +# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. -Serial number (magic cookie) for the routing is: -11536 +Serial number (magic cookie) for the routing is: -18854 Circuit successfully routed with a channel width factor of 40. -Average number of bends per net: 0.333333 Maximum # of bends: 1 +Average number of bends per net: 2.00000 Maximum # of bends: 3 Number of global nets: 0 Number of routed nets (nonglobal): 3 Wire length results (in units of 1 clb segments)... - Total wirelength: 6, average net length: 2.00000 - Maximum net length: 3 + Total wirelength: 12, average net length: 4.00000 + Maximum net length: 6 Wire length results in terms of physical segments... - Total wiring segments used: 5, average wire segments per net: 1.66667 - Maximum segments used by a net: 2 + Total wiring segments used: 9, average wire segments per net: 3.00000 + Maximum segments used by a net: 4 Total local nets with reserved CLB opins: 0 Routing channel utilization histogram: @@ -510,17 +496,17 @@ Routing channel utilization histogram: [ 0.2: 0.3) 0 ( 0.0%) | [ 0.1: 0.2) 0 ( 0.0%) | [ 0: 0.1) 18 (100.0%) |************************************************ -Maximum routing channel utilization: 0.075 at (1,0) +Maximum routing channel utilization: 0.05 at (1,0) X - Directed channels: j max occ ave occ capacity ---- ------- ------- -------- - 0 3 1.250 40 - 1 0 0.000 40 + 0 2 0.750 40 + 1 2 0.500 40 2 0 0.000 40 Y - Directed channels: i max occ ave occ capacity ---- ------- ------- -------- - 0 1 0.250 40 - 1 0 0.000 40 + 0 2 0.750 40 + 1 3 1.000 40 2 0 0.000 40 Total tracks in x-direction: 120, in y-direction: 120 @@ -530,55 +516,55 @@ Logic area (in minimum width transistor areas, excludes I/Os and empty grid tile Total used logic block area: 53894 Routing area (in minimum width transistor areas)... - Total routing area: 22261.4, per logic tile: 1391.34 + Total routing area: 23072.6, per logic tile: 1442.04 Segment usage by type (index): type utilization ---- ----------- 0 0.0833 - 1 0.0278 - 2 0 + 1 0 + 2 0.0208 Segment usage by length: length utilization ------ ----------- 1 0.0833 - 2 0.0278 - 4 0 + 2 0 + 4 0.0208 Hold Worst Negative Slack (hWNS): 0 ns Hold Total Negative Slack (hTNS): 0 ns Hold slack histogram: -[ 5.5e-10: 5.5e-10) 1 (100.0%) |************************************************** -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 1 (100.0%) |************************************************** +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -Final critical path: 0.69331 ns, Fmax: 1442.36 MHz -Setup Worst Negative Slack (sWNS): -0.69331 ns -Setup Total Negative Slack (sTNS): -0.69331 ns +Final critical path: 0.86731 ns, Fmax: 1152.99 MHz +Setup Worst Negative Slack (sWNS): -0.86731 ns +Setup Total Negative Slack (sTNS): -0.86731 ns Setup slack histogram: -[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 1 (100.0%) |************************************************** +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -Timing analysis took 0.000488774 seconds (0.000430824 STA, 5.795e-05 slack) (80 full updates: 78 setup, 0 hold, 2 combined). +Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). VPR suceeded -The entire flow of VPR took 0.08 seconds (max_rss 11.9 MiB) +The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -586,17 +572,16 @@ Confirm selected options when call command 'read_openfpga_arch': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... Read OpenFPGA architecture -Warning 47: Automatically set circuit model 'frac_lut4' to be default in its type. -Warning 48: Automatically set circuit model 'sky130_fd_sc_hd__sdfxbp_1' to be default in its type. -Warning 49: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. -Warning 50: Automatically set circuit model 'GPIO' to be default in its type. +Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type. +Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type. +Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') -Read OpenFPGA architecture took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.3 MiB) +Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB) Check circuit library Checking circuit library passed. -Check circuit library took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Found 0 errors when checking configurable memory circuit models! Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml @@ -605,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Read OpenFPGA simulation settings -Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges @@ -634,9 +619,9 @@ Check pb_graph annotation for physical nodes and pins passed. Binded 4 routing resource graph switches to circuit models Binded 3 routing segments to circuit models Binded 2 direct connections to circuit models -Annotating rr_node with routed nets...Done with 11 nodes mapping -Annotating previous nodes for rr_node...Warning 51: Override the previous node '89' by previous node '90' for node '37' with in routing context annotation! -Done with 14 nodes mapping +Annotating rr_node with routed nets...Done with 15 nodes mapping +Annotating previous nodes for rr_node...Warning 55: Override the previous node '139' by previous node '137' for node '84' with in routing context annotation! +Done with 18 nodes mapping # Build General Switch Block(GSB) annotation on top of routing resource graph [11%] Backannotated GSB[0][0] [22%] Backannotated GSB[0][1] @@ -648,7 +633,7 @@ Done with 14 nodes mapping [88%] Backannotated GSB[2][1] [100%] Backannotated GSB[2][2] Backannotated 9 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [11%] Sorted edges for GSB[0][0] [22%] Sorted edges for GSB[0][1] @@ -660,9 +645,9 @@ Backannotated 9 General Switch Blocks (GSBs). [88%] Sorted edges for GSB[2][1] [100%] Sorted edges for GSB[2][2] Sorted edges for 9 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Build a library of physical multiplexers -Built a multiplexer library of 14 physical multiplexers. +Built a multiplexer library of 15 physical multiplexers. Maximum multiplexer size is 17. # Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) # Build the annotation about direct connection between tiles @@ -670,8 +655,8 @@ Built 6 tile-to-tile direct connections # Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) Building annotation for mapped blocks on grid locations...Done User specified the operating clock frequency to use VPR results -Use VPR critical path delay 8.31972e-19 [ns] with a 20 [%] slack in OpenFPGA. -Will apply operating clock frequency 1201.96 [MHz] to simulations +Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA. +Will apply operating clock frequency 960.825 [MHz] to simulations User specified the number of operating clock cycles to be inferred from signal activities Average net density: 0.42 Median net density: 0.00 @@ -694,63 +679,65 @@ Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00 Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) Read Fabric Key -Read Fabric Key took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Build fabric module graph # Build constant generator modules -# Build constant generator modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build constant generator modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build user-defined modules -# Build user-defined modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build user-defined modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build essential (inverter/buffer/logic gate) modules -# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build local encoder (for multiplexers) modules -# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Building multiplexer modules -# Building multiplexer modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.3 MiB) +# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) # Build Look-Up Table (LUT) modules -# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) +# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB) # Build wire modules -# Build wire modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) +# Build wire modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) # Build memory modules -# Build memory modules took 0.00 seconds (max_rss 13.1 MiB, delta_rss +0.3 MiB) +# Build memory modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) # Build grid modules Building logical tiles...Done Building physical tiles...Done -# Build grid modules took 0.00 seconds (max_rss 13.6 MiB, delta_rss +0.5 MiB) +# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB) # Build unique routing modules... -# Build unique routing modules... took 0.01 seconds (max_rss 15.9 MiB, delta_rss +2.3 MiB) +# Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB) # Build FPGA fabric module ## Add grid instances to top module -## Add grid instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add switch block instances to top module -## Add switch block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add switch block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.5 MiB) +## Add module nets between grids and GSBs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.5 MiB) ## Add module nets for inter-tile connections -## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.0 MiB) +## Add module nets for inter-tile connections took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) ## Add module nets for configuration buses -## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.1 MiB) -# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +0.9 MiB) -Build fabric module graph took 0.02 seconds (max_rss 16.8 MiB, delta_rss +4.2 MiB) +## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB) +Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB) +Create I/O location mapping for top module +Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Command line to execute: repack Confirm selected options when call command 'repack': --verbose: off Build routing resource graph for the physical implementation of logical tile -Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.3 MiB) +Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) Repack clustered blocks to physical implementation of logical tile Repack clustered block 'c'...Done Repack clustered block 'out:c'...Done Repack clustered block 'a'...Done Repack clustered block 'b'...Done -Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) +Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) Build truth tables for physical LUTs -Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) +Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB) Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml @@ -766,10 +753,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) -Warning 52: Directory path is empty and nothing will be created. -Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) +Warning 56: Directory path is empty and nothing will be created. +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -780,7 +767,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.3 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -788,9 +775,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.bit --format: plain_text --verbose: off -Warning 53: Directory path is empty and nothing will be created. -Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +Warning 57: Directory path is empty and nothing will be created. +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml @@ -798,9 +785,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.xml --format: xml --verbose: off -Warning 54: Directory path is empty and nothing will be created. -Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +Warning 58: Directory path is empty and nothing will be created. +Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' +Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose @@ -852,22 +839,23 @@ Done Writing logical tiles...Done Building physical tiles... -Writing Verilog Netlist './SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done -Written 70 Verilog modules in total +Written 73 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.15 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) + took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping Confirm selected options when call command 'write_verilog_testbench': --file, -f: ./SRC +--fabric_netlist_file_path: off --reference_benchmark_file_path: top_output_verilog.v --print_top_testbench: on --fast_configuration: off @@ -876,22 +864,22 @@ Confirm selected options when call command 'write_verilog_testbench': --print_simulation_ini: ./SimulationDeck/simulation_deck.ini --explicit_port_mapping: on --verbose: off -Warning 55: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled +Warning 59: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled Write Verilog testbenches for FPGA fabric -Warning 56: Directory './SRC' already exists. Will overwrite contents +Warning 60: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' -Will use 2010 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +Will use 2107 configuration clock cycles to top testbench +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 0.03 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) + took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -899,6 +887,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 0.22 seconds +The entire OpenFPGA flow took 0.25 seconds Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml index 1f3d05a..47f4507 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml @@ -1,36 +1,38 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml index 2f3088b..5b8d71e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml @@ -148,7 +148,7 @@ - + @@ -174,27 +174,25 @@ - + - - + - - - - - - - + + + + + + @@ -220,20 +218,16 @@ - + - - - - - + @@ -252,4 +246,4 @@ - + \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml index 536b9fc..843bc0f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml @@ -33,7 +33,7 @@ - + @@ -60,7 +60,8 @@ If you need to register the I/O, define clocks in the circuit models These clocks can be handled in back-end --> - + + @@ -68,72 +69,117 @@ - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad + io_top.outpad io_top.inpad + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + - - - - - - - - + + + + + + + + + + + + + + + + - + - + - - + + + clb.clk - clb.regin clb.scin - clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3 - clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7 + clb.regin clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.regout clb.sc_out - + - + + + + - + + + + - + - - - - - - - - + + + + @@ -210,12 +256,10 @@ - + - - - + @@ -266,39 +310,37 @@ - - - - + - - - - - - - - + + + + + + + + + + + + + + + + - + - + - + - + @@ -350,9 +392,9 @@ - + - + @@ -375,10 +417,10 @@ - + - + @@ -534,30 +576,56 @@ - - + + + - + + - + + - + + - + + - + + - + + - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -581,13 +649,13 @@ - + - + - + - + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v new file mode 100644 index 0000000..0dcc04f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v @@ -0,0 +1,63 @@ +`timescale 1ns/1ps + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule + + +// +// +// +// +module EMBEDDED_IO ( + input SOC_IN, // + output SOC_OUT, // + output SOC_DIR, // + output FPGA_IN, // + input FPGA_OUT, // + input FPGA_DIR // +); + + assign FPGA_IN = SOC_IN; + assign SOC_OUT = FPGA_OUT; + assign SOC_DIR = FPGA_DIR; +endmodule + +// +// +// +module GPIN ( + inout A, // + output Y // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule + +// +// +// +module GPOUT ( + inout Y, // + input A // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/README.md b/FPGA22_HIER_SKY_PNR/README.md index bc7be12..0c9ee97 100644 --- a/FPGA22_HIER_SKY_PNR/README.md +++ b/FPGA22_HIER_SKY_PNR/README.md @@ -2,7 +2,14 @@ FPGA22_HIER_SKY_PNR ==================== 2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`. -Utilization set to 60% + +Updates +------------------- +- **Merged `grid_io` modules with connection blocks** +- **Pre-routed scan chain signals** +- **Created `carry_chain` feedthrough between `grid_clb` modules** +- Prerouting global signals (`Test_en`) +- Prerouting clock signals Directory Structure ------------------- @@ -21,4 +28,4 @@ Pending --------- - DRC SignOff - LVS SignOff -- PostPnR function simulation +- PostPnR functional simulation diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png index fbe96c5b39d68707cef813dd6a2c3124e90e2323..9e0d25cad2f2ac640e3dcf2cf11728920b290d43 100644 GIT binary patch literal 67614 zcmeFZbyStz7BBn&0!oNTNC^niDXB=kNOz}%bR*rceMRX|xWrAf^LJCx1rm} z;3Ci_Y6dQMUQ22@LJ-a?#2-?wP>uxzQ9@Fpf2g`8ZO?j+kU4t`?e(|&y$+@fLdMV& z#-7U!Qs>fxp4s4keJj22<6YI*RIor50aJ{~sTw0A)m&F;mR^R#-uqa^w+TyGfqwT4 zB_UMQOjvb>19O^rtyQA)_3TvhiLbjw ziF?W0eLmmMFN@Dt?)xg&_Yv?{RpB71(D}3aG!8@4pq<>Oa)zYmkU2@Opxna(zkISH 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