mirror of https://github.com/lnis-uofu/SOFA.git
164 lines
5.8 KiB
Coq
164 lines
5.8 KiB
Coq
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/*
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*-------------------------------------------------------------
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*
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* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
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*
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* This wrapper is a behavioral modeling the FPGA I/O interface
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* to the Caravel SoC
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*
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* It should be synthesized before sent for physical design implementation
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*
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*-------------------------------------------------------------
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*/
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module caravel_fpga_wrapper (
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// Fixed I/O interface from Caravel SoC definition
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// DO NOT CHANGE!!!
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oen,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb
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);
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wire [`MPRJ_IO_PADS-1:0] io_in;
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wire [`MPRJ_IO_PADS-1:0] io_out;
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wire [`MPRJ_IO_PADS-1:0] io_oeb;
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// FPGA wires
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wire prog_clk;
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wire Test_en;
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wire io_isol_n;
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wire clk;
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_IN;
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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wire ccff_head;
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wire ccff_tail;
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wire sc_head;
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wire sc_tail;
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// Switch between wishbone and logic analyzer
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wire wb_la_switch;
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// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = io_in[24];
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assign io_out[24] = gfpga_pad_EMBEDDED_IO_SOC_OUT[0];
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assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_SOC_DIR[0];
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// Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[1:9] = io_in[23:15];
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assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_SOC_OUT[1:9];
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assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_SOC_DIR[1:9];
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// Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[10:11] = io_in[14:13];
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assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10:11];
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assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_SOC_DIR[10:11];
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// Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface
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assign ccff_head = io_in[12];
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assign io_out[12] = 1'b0;
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assign io_oeb[12] = 1'b1;
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assign io_out[11] = sc_tail;
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assign io_oeb[11] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[12:20] = io_in[10:2];
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assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_SOC_OUT[12:20];
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assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_SOC_DIR[12:20];
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assign io_isol_n = io_in[1];
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assign io_out[1] = 1'b0;
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assign io_oeb[1] = 1'b1;
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assign Test_en = io_in[0];
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assign io_out[0] = 1'b0;
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assign io_oeb[0] = 1'b1;
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// Wire-bond RIGHT side I/O of FPGA to BOTTOM-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[21] = la_wb_switch ? wb_rst_i : la_data_in[0];
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[22] = la_wb_switch ? wb_stb_i : la_data_in[1];
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[23] = la_wb_switch ? wb_cyc_i : la_data_in[2];
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assign la_data_out[0:2] = gfpga_pad_EMBEDDED_IO_SOC_OUT[21:23];
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// Wire-bond BOTTOM side I/O of FPGA to BOTTOM-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[24] = la_wb_switch ? wb_we_i : la_data_in[3];
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[25:56] = la_wb_switch ? wb_dat_i : la_data_in[4:35];
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[57:88] = la_wb_switch ? wb_adr_i : la_data_in[36:67];
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assign wb_ack_o = gfpga_pad_EMBEDDED_IO_SOC_OUT[89];
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assign wb_data_o = gfpga_pad_EMBEDDED_IO_SOC_OUT[90:121];
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assign la_data_out[3:110] = gfpga_pad_EMBEDDED_IO_SOC_OUT[24:131];
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// Wire-bond LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[132:135] = la_wb_switch ? wb_sel_i : la_data_in[111:114];
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assign la_data_out[111:114] = gfpga_pad_EMBEDDED_IO_SOC_OUT[132:135];
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// Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface
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assign prog_clk = io_in[37];
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assign io_out[37] = 1'b0;
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assign io_oeb[37] = 1'b1;
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assign clk = io_in[36];
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assign io_out[36] = 1'b0;
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assign io_oeb[36] = 1'b1;
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assign io_out[35] = ccff_tail;
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assign io_oeb[35] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[136:143] = io_in[34:27];
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assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_SOC_OUT[136:143];
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assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_SOC_DIR[136:143];
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assign sc_in = io_in[26];
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assign io_out[26] = 1'b0;
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assign io_oeb[26] = 1'b1;
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// I/O[25] is reserved for a switch between wishbone interface
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// and logic analyzer
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assign wb_la_switch = io_in[25];
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assign io_out[25] = 1'b0;
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assign io_oeb[25] = 1'b1;
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// TODO: Connect spypad from FPGA to logic analyzer ports
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fpga_core fpga_core(.prog_clk(prog_clk),
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.Test_en(Test_en),
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.clk(clk),
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.IO_ISOL_N(io_isol_n),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR),
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.ccff_head(ccff_head),
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.ccff_tail(ccff_tail),
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.sc_head(sc_head),
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.sc_tail(sc_tail)
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);
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endmodule
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