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tangxifan d36cb8abe7 [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script 2020-11-17 21:44:13 -07:00
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common [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script 2020-11-17 21:44:13 -07:00
README.md [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA. It also includes necessary wrappers to enable the netlist generation. The custom netlists are place in the common directory.