tangxifan d36cb8abe7 [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script		2020-11-17 21:44:13 -07:00
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caravel_fpga_wrapper_behavioral.v	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00
caravel_fpga_wrapper_hd.v	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00
digital_io_behavorial.v	[HDL] Add digitial I/O with protection circuitry	2020-11-17 19:17:48 -07:00
digital_io_hd.v	[HDL] Bug fix in I/O cell	2020-11-17 20:03:20 -07:00
skywater_function_verification.v	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00
wrapper_lines_generator.py	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00