2020-11-29 21:23:34 -06:00
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#####################################################################
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# Python script to convert a post-PnR Verilog testbench
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# to a post-PnR Verilog testbench based on Caravel Wrapper
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# This script will
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# - Replace the FPGA instance with a Caravel wrapper instance
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# - Generate wrapper input ports based on a pin assignment json file
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#####################################################################
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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import re
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import argparse
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import logging
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import json
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Converter for post-PnR wrapper Verilog testbench')
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parser.add_argument('--post_pnr_testbench', required=True,
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help='Specify the file path for the post-PnR Verilog testbench as input')
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parser.add_argument('--pin_assignment_file', required=True,
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help='Specify the file path to the pin assignment JSON description as input')
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parser.add_argument('--wrapper_testbench', required=True,
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help='Specify the file path for the post-PnR wrapper Verilog testbench to be outputted')
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args = parser.parse_args()
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#####################################################################
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# Check options:
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# - Input file must be valid
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# Otherwise, error out
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# - Remove any output file if already exist
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# TODO: give a warning when remove files
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#####################################################################
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if not isfile(args.post_pnr_testbench):
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logging.error("Invalid pre-PnR testbench: " + args.post_pnr_testbench + "\nFile does not exist!\n")
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exit(1)
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if not isfile(args.pin_assignment_file):
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logging.error("Invalid pin assignment file: " + args.pin_assignment_file + "\nFile does not exist!\n")
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exit(1)
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if isfile(args.wrapper_testbench):
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logging.warn("Remove existing post-PnR testbench: " + args.wrapper_testbench + "!\n")
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os.remove(args.wrapper_testbench)
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#####################################################################
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# Parse the json file
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#####################################################################
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json_file = open(args.pin_assignment_file, "r")
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pin_data = json.load(json_file)
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#####################################################################
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# TODO: This is a duplicated function from the wrapper_lines_generator.py
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# Should merge them and make it shareable between scripts
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# A function to parse pin range from json data
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# JSON pin range format is LSB:MSB
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# Return pin range format is [LSB, MSB] as a list
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#####################################################################
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def parse_json_pin_range(json_range) :
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pin_range_str = json_range.split(':')
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assert(2 == len(pin_range_str))
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# If the range is in decend order, we will decrease the MSB by 1
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if (int(pin_range_str[0]) > int(pin_range_str[1])) :
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return range(int(pin_range_str[0]), int(pin_range_str[1]) - 1, -1)
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# If the range is in acend order, we will increase the MSB by 1
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return range(int(pin_range_str[0]), int(pin_range_str[1]) + 1)
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#####################################################################
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# Write the connections between wrapper ports and existing stimuli
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# to the testbench file
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#####################################################################
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def write_testbench_wrapper_connection(tb_file, pin_data, mode_switch_io_index):
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# Switch to the logic analyzer mode for io[25] which is reserved for mode-switch purpose
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mode_switch_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(mode_switch_io_index) + "] = " \
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2020-11-29 21:32:59 -06:00
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+ "1'b0;";
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2020-11-29 21:23:34 -06:00
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tb_file.write(" " + mode_switch_line + "\n")
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for pin_info in pin_data['pins']:
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#######################################################
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# For FPGA INPUTs,
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# wrapper inputs should be driven these existing wires
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# For instance:
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# assign wrapper_input = FPGA_INPUT;
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#
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# For FPGA OUTPUTs,
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# wrapper outputs should drive these existing wires
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# For instance:
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# assign FPGA_OUTPUT = wrapper_output;
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# - FPGA I/O ports to Caravel GPIO
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if (("io" == pin_info['fpga_pin_type']) \
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and (1 == len(pin_info['caravel_pin_type'])) \
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and ("gpio" == pin_info['caravel_pin_type'][0])):
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# Should have only 1 port in caravel
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assert(1 == len(pin_info['caravel_pin_type']))
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assert(1 == len(pin_info['caravel_pin_index']))
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# Get pin range
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fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index'])
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caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0])
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assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range)))
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for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) :
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# FPGA input <- Caravel input
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curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \
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+ pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "];";
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tb_file.write(" " + curr_line + "\n")
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# FPGA output -> Caravel output
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curr_line = "assign " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "] = " \
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+ pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];";
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tb_file.write(" " + curr_line + "\n")
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# FPGA direction -> Caravel direction
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curr_line = "assign " + pin_data['fpga_gpio_direction_name'] + "[" + str(indices[0]) + "] = " \
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+ pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "];";
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tb_file.write(" " + curr_line + "\n")
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# - FPGA control input ports to Caravel GPIO
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if (("io" != pin_info['fpga_pin_type']) \
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and (1 == len(pin_info['caravel_pin_type'])) \
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and ("input" == pin_info['caravel_pin_type'][0])):
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# Should have only 1 port in caravel
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assert(1 == len(pin_info['caravel_pin_type']))
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assert(1 == len(pin_info['caravel_pin_index']))
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# Get pin range
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fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index'])
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caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0])
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assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range)))
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for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) :
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# Connect the FPGA input port to the Caravel input
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2020-11-29 21:31:19 -06:00
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curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = " \
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+ pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "];";
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2020-11-29 21:23:34 -06:00
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tb_file.write(" " + curr_line + "\n")
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# - FPGA control output ports to Caravel GPIO
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if (("io" != pin_info['fpga_pin_type']) \
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and (1 == len(pin_info['caravel_pin_type'])) \
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and ("output" == pin_info['caravel_pin_type'][0])):
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# Should have only 1 port in caravel
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assert(1 == len(pin_info['caravel_pin_type']))
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assert(1 == len(pin_info['caravel_pin_index']))
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# Get pin range
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fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index'])
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caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0])
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assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range)))
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for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) :
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# Tie the Caravel input to logic '0'
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curr_line = "assign " + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "] = 1'b0;"
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tb_file.write(" " + curr_line + "\n")
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# Connect Caravel output port to FPGA control output
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2020-11-29 21:31:19 -06:00
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curr_line = "assign " + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \
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+ pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "];";
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2020-11-29 21:23:34 -06:00
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tb_file.write(" " + curr_line + "\n")
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# - We always try to use the logic analyzer to connect FPGA I/O ports
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if (("io" == pin_info['fpga_pin_type']) \
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and ("logic_analyzer_io" == pin_info['caravel_pin_type'][0])):
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# Get pin range
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fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index'])
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caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0])
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assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range)))
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for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) :
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##############################################################
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# SOC INPUT will be directly driven by logic analyzer
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# since this I/O is going to interface logic analyzer input only
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curr_line = "assign " + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "] = " \
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+ pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "]" + ";"
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tb_file.write(" " + curr_line + "\n")
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##############################################################
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# SOC OUTPUT will directly drive logic analyzer
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# since this I/O is going to interface logic analyzer output only
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curr_line = "assign " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]" \
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+ " = " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "];"
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tb_file.write(" " + curr_line + "\n")
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#####################################################################
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# Open the post-pnr Verilog testbench and start modification
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#####################################################################
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logging.info("Converting post-PnR testbench:"+ args.post_pnr_testbench)
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2020-11-29 21:31:19 -06:00
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logging.info("To post-PnR wrapper testbench:"+ args.wrapper_testbench)
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2020-11-29 21:23:34 -06:00
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# Create output file handler
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tb_file = open(args.wrapper_testbench, "w")
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#################################
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# Control signals to output lines
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# Skip current line: when raised, current line will not be outputted
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skip_current_line = False
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fpga_instance_lines = False
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# Read line by line from pre-PnR testbench
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with open(args.post_pnr_testbench, "r") as wp:
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template_netlist = wp.readlines()
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for line_num, curr_line in enumerate(template_netlist):
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# If the current line satisfy the following conditions
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# It should be modified and outputted to post-PnR Verilog testbenches
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# Other lines can be directly copied to post-PnR Verilog testbenches
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line2output = curr_line
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#
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# Add post_pnr to top-level module name
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if (curr_line.startswith("module")):
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line2output = re.sub("autocheck_top_tb;$", "wrapper_autocheck_top_tb;", curr_line)
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# Add the wires required by the wrapper
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if (curr_line == "wire [0:0] sc_tail;\n"):
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line2output = line2output \
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+ "// ---- Wrapper I/O wires ----\n" \
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+ "// ---- Power pins ----\n" \
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+ "wire [0:0] vdda1;\n" \
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+ "wire [0:0] vdda2;\n" \
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+ "wire [0:0] vssa1;\n" \
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+ "wire [0:0] vssa2;\n" \
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+ "wire [0:0] vccd1;\n" \
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+ "wire [0:0] vccd2;\n" \
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+ "wire [0:0] vssd1;\n" \
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+ "wire [0:0] vssd2;\n" \
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+ "// ---- Wishbone pins ----\n" \
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+ "wire [0:0] wb_clk_i;\n" \
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+ "wire [0:0] wb_rst_i;\n" \
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+ "wire [0:0] wbs_stb_i;\n" \
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+ "wire [0:0] wbs_cyc_i;\n" \
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+ "wire [0:0] wbs_we_i;\n" \
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+ "wire [3:0] wbs_sel_i;\n" \
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+ "wire [31:0] wbs_dat_i;\n" \
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+ "wire [31:0] wbs_adr_i;\n" \
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+ "wire [0:0] wbs_ack_o;\n" \
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+ "wire [31:0] wbs_dat_o;\n" \
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+ "// ---- Logic analyzer pins ----\n" \
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+ "wire [127:0] la_data_in;\n" \
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+ "wire [127:0] la_data_out;\n" \
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+ "wire [127:0] la_oen;\n" \
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+ "// ---- GPIO pins ----\n" \
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2020-11-29 22:15:36 -06:00
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+ "wire [`MPRJ_IO_PADS-1:0] io_in;\n" \
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+ "wire [`MPRJ_IO_PADS-1:0] io_out;\n" \
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+ "wire [`MPRJ_IO_PADS-1:0] io_oeb;\n" \
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+ "// ---- Analog I/O pins ----\n" \
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+ "wire [`MPRJ_IO_PADS-8:0] analog_io;\n" \
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2020-11-29 23:20:15 -06:00
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+ "// ---- User clock pin ----\n" \
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+ "wire [0:0] user_clock2;\n"
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2020-11-29 23:32:36 -06:00
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# TODO: This is a temporary fix for the flattened analog io port
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# SHOULD BE REMOVED ABOUT UPDATED WRAPPER
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for ipin in range(31):
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line2output += "wire [0:0] analog_io_" + str(ipin) + "_;\n"
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# Skip all the lines about FPGA instanciation
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if (curr_line == "\tfpga_core FPGA_DUT (\n"):
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skip_current_line = True
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fpga_instance_lines = True
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# When FPGA instance are skipped, add the wrapper instance
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if ((True == fpga_instance_lines) and (curr_line.endswith(");\n"))):
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skip_current_line = False
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fpga_instance_lines = False
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2020-11-29 22:19:56 -06:00
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line2output = "\tfpga_top FPGA_DUT(\n" \
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2020-11-29 21:23:34 -06:00
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+ "\t\t\t.vdda1(vdda1),\n" \
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+ "\t\t\t.vdda2(vdda2),\n" \
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+ "\t\t\t.vssa1(vssa1),\n" \
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+ "\t\t\t.vssa2(vssa2),\n" \
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+ "\t\t\t.vccd1(vccd1),\n" \
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+ "\t\t\t.vccd2(vccd2),\n" \
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+ "\t\t\t.vssd1(vssd1),\n" \
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+ "\t\t\t.vssd2(vssd2),\n" \
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+ "\t\t\t.wb_clk_i(wb_clk_i),\n" \
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+ "\t\t\t.wb_rst_i(wb_rst_i),\n" \
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+ "\t\t\t.wbs_stb_i(wbs_stb_i),\n" \
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2020-11-29 23:17:10 -06:00
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+ "\t\t\t.wbs_we_i(wbs_we_i),\n" \
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2020-11-29 21:23:34 -06:00
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+ "\t\t\t.wbs_cyc_i(wbs_cyc_i),\n" \
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+ "\t\t\t.wbs_sel_i(wbs_sel_i),\n" \
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+ "\t\t\t.wbs_dat_i(wbs_dat_i),\n" \
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+ "\t\t\t.wbs_adr_i(wbs_adr_i),\n" \
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+ "\t\t\t.wbs_ack_o(wbs_ack_o),\n" \
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+ "\t\t\t.wbs_dat_o(wbs_dat_o),\n" \
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+ "\t\t\t.la_data_in(la_data_in),\n" \
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+ "\t\t\t.la_data_out(la_data_out),\n" \
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+ "\t\t\t.la_oen(la_oen),\n" \
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+ "\t\t\t.io_in(io_in),\n" \
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+ "\t\t\t.io_out(io_out),\n" \
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+ "\t\t\t.io_oeb(io_oeb),\n" \
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2020-11-29 23:32:36 -06:00
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#+ "\t\t\t.analog_io(analog_io),\n" \
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#+ "\t\t\t);\n";
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# TODO: This is a temporary fix for the flattened analog io port
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# SHOULD BE REMOVED ABOUT UPDATED WRAPPER
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for ipin in range(31):
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line2output += ".analog_io_" + str(ipin) + "_(analog_io_" + str(ipin) + "_),\n"
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line2output += "\t\t\t.user_clock2(user_clock2)\n"
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line2output += "\t\t\t);\n";
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2020-11-29 21:31:19 -06:00
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# Wire the stimuli according to pin assignment
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write_testbench_wrapper_connection(tb_file, pin_data, 25)
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2020-11-29 22:44:29 -06:00
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# Correct the path in signal initialization
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if (re.search(r'\$deposit\(FPGA_DUT', curr_line)):
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line2output = re.sub(r'\$deposit\(FPGA_DUT', '$deposit(FPGA_DUT.fpga_core_uut', curr_line)
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2020-11-29 21:23:34 -06:00
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if (False == skip_current_line):
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tb_file.write(line2output)
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tb_file.close()
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logging.info("Done")
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