tangxifan 92a3a444f9 update VPR7 to support global I/O ports		2020-04-06 20:44:00 -06:00
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backend_assistant	update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA	2020-03-25 14:44:42 -06:00
base	update VPR7 to support global I/O ports	2020-04-06 20:44:00 -06:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	update VPR7 to support global I/O ports	2020-04-06 20:44:00 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	deleting legacy codes: fpga_verilog top-level function	2019-12-04 15:55:16 -07:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	update VPR7 to support global I/O ports	2020-04-06 20:44:00 -06:00