Yitian4Debug a1169beaf0 Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name ... To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.		2023-12-04 13:34:49 -08:00
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arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[test] deploy new tests	2023-07-08 21:52:16 -07:00
misc	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
openfpga_arch	[test] fixed a bug	2023-09-25 19:28:19 -07:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] add a new test case to validate the new feature	2023-11-02 21:08:36 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	[test] add new testcase	2023-11-13 14:11:34 -08:00
scripts	[test] reworking adder mapping flow to validate carry chain mapping	2023-06-20 16:57:08 -07:00
tasks	Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name	2023-12-04 13:34:49 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[test] enable missing options in the arch used by benchmark sweeping tests	2023-11-14 09:45:02 -08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00