436 lines
21 KiB
C++
436 lines
21 KiB
C++
/********************************************************************
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* This file includes functions that are used to print the top-level
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* module for the FPGA fabric in Verilog format
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*******************************************************************/
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#include <map>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "module_manager_utils.h"
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#include "build_top_module_utils.h"
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#include "build_top_module_connection.h"
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#include "build_top_module_memory.h"
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#include "build_top_module_directs.h"
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#include "build_module_graph_utils.h"
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#include "openfpga_device_grid_utils.h"
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#include "build_top_module.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Add a instance of a grid module to the top module
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*******************************************************************/
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static
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size_t add_top_module_grid_instance(ModuleManager& module_manager,
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const ModuleId& top_module,
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t_physical_tile_type_ptr grid_type,
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const e_side& border_side,
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const vtr::Point<size_t>& grid_coord) {
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/* Find the module name for this type of grid */
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Record the instance id */
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size_t grid_instance = module_manager.num_instance(top_module, grid_module);
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/* Add the module to top_module */
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module_manager.add_child_module(top_module, grid_module);
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/* Set an unique name to the instance
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* Note: it is your risk to gurantee the name is unique!
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*/
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std::string instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side, grid_coord);
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module_manager.set_child_instance_name(top_module, grid_module, grid_instance, instance_name);
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return grid_instance;
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}
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/********************************************************************
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* Add all the grids as sub-modules across the fabric
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* The grid modules are created for each unique type of grid (based
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* on the type in data structure data_structure
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* Here, we will iterate over the full fabric (coordinates)
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* and instanciate the grid modules
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*
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* Return an 2-D array of instance ids of the grid modules that
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* have been added
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*
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* This function assumes an island-style floorplanning for FPGA fabric
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*
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*
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* +-----------------------------------+
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* | I/O grids |
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* | TOP side |
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* +-----------------------------------+
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*
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* +-----------+ +-----------------------------------+ +------------+
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* | | | | | |
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* | I/O grids | | Core grids | | I/O grids |
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* | LEFT side | | (CLB, Heterogeneous blocks, etc.) | | RIGHT side |
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* | | | | | |
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* +-----------+ +-----------------------------------+ +------------+
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*
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* +-----------------------------------+
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* | I/O grids |
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* | BOTTOM side |
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* +-----------------------------------+
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*
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*******************************************************************/
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static
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vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
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const ModuleId& top_module,
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const DeviceGrid& grids) {
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vtr::ScopedStartFinishTimer timer("Add grid instances to top module");
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/* Reserve an array for the instance ids */
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vtr::Matrix<size_t> grid_instance_ids({grids.width(), grids.height()});
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grid_instance_ids.fill(size_t(-1));
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/* Instanciate core grids */
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
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/* Bypass EMPTY grid */
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if (true == is_empty_type(grids[ix][iy].type)) {
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continue;
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}
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/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
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if ( (0 < grids[ix][iy].width_offset)
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|| (0 < grids[ix][iy].height_offset)) {
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/* Find the root of this grid, the instance id should be valid.
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* We just copy it here
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*/
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vtr::Point<size_t> root_grid_coord(ix - grids[ix][iy].width_offset,
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iy - grids[ix][iy].height_offset);
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VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
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grid_instance_ids[ix][iy] = grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()];
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continue;
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}
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/* Add a grid module to top_module*/
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vtr::Point<size_t> grid_coord(ix, iy);
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grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module,
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grids[ix][iy].type,
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NUM_SIDES, grid_coord);
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}
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}
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/* Instanciate I/O grids */
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/* Create the coordinate range for each side of FPGA fabric */
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std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates = generate_perimeter_grid_coordinates( grids);
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for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
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for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
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/* Bypass EMPTY grid */
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if (true == is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
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continue;
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}
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/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
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if ( (0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset)
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|| (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
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/* Find the root of this grid, the instance id should be valid.
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* We just copy it here
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*/
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vtr::Point<size_t> root_grid_coord(io_coordinate.x() - grids[io_coordinate.x()][io_coordinate.y()].width_offset,
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io_coordinate.y() - grids[io_coordinate.x()][io_coordinate.y()].height_offset);
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VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
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grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()];
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continue;
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}
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/* Add a grid module to top_module*/
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grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate);
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}
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}
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return grid_instance_ids;
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}
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/********************************************************************
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* Add switch blocks across the FPGA fabric to the top-level module
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* Return an 2-D array of instance ids of the switch blocks that
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* have been added
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*******************************************************************/
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static
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vtr::Matrix<size_t> add_top_module_switch_block_instances(ModuleManager& module_manager,
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const ModuleId& top_module,
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const DeviceRRGSB& device_rr_gsb,
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const bool& compact_routing_hierarchy) {
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vtr::ScopedStartFinishTimer timer("Add switch block instances to top module");
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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/* Reserve an array for the instance ids */
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vtr::Matrix<size_t> sb_instance_ids({sb_range.x(), sb_range.y()});
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sb_instance_ids.fill(size_t(-1));
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for (size_t ix = 0; ix < sb_range.x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.y(); ++iy) {
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/* If we use compact routing hierarchy, we should instanciate the unique module of SB */
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if ( false == rr_gsb.is_sb_exist() ) {
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continue;
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}
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vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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if (true == compact_routing_hierarchy) {
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vtr::Point<size_t> sb_coord(ix, iy);
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
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sb_coordinate.set_x(unique_mirror.get_sb_x());
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sb_coordinate.set_y(unique_mirror.get_sb_y());
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}
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std::string sb_module_name = generate_switch_block_module_name(sb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Record the instance id */
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sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module);
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/* Add the module to top_module */
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module_manager.add_child_module(top_module, sb_module);
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/* Set an unique name to the instance
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* Note: it is your risk to gurantee the name is unique!
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*/
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module_manager.set_child_instance_name(top_module, sb_module,
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sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()],
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generate_switch_block_module_name(vtr::Point<size_t>(rr_gsb.get_sb_x(), rr_gsb.get_sb_y())));
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}
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}
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return sb_instance_ids;
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}
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/********************************************************************
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* Add switch blocks across the FPGA fabric to the top-level module
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*******************************************************************/
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static
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vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& module_manager,
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const ModuleId& top_module,
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const DeviceRRGSB& device_rr_gsb,
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const t_rr_type& cb_type,
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const bool& compact_routing_hierarchy) {
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vtr::ScopedStartFinishTimer timer("Add connection block instances to top module");
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vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
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/* Reserve an array for the instance ids */
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vtr::Matrix<size_t> cb_instance_ids({cb_range.x(), cb_range.y()});
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cb_instance_ids.fill(size_t(-1));
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for (size_t ix = 0; ix < cb_range.x(); ++ix) {
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for (size_t iy = 0; iy < cb_range.y(); ++iy) {
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/* Check if the connection block exists in the device!
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* Some of them do NOT exist due to heterogeneous blocks (height > 1)
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* We will skip those modules
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*/
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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if ( false == rr_gsb.is_cb_exist(cb_type) ) {
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continue;
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}
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/* If we use compact routing hierarchy, we should instanciate the unique module of SB */
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if (true == compact_routing_hierarchy) {
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vtr::Point<size_t> cb_coord(ix, iy);
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
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cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type));
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cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type));
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}
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std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate);
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ModuleId cb_module = module_manager.find_module(cb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Record the instance id */
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cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module);
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/* Add the module to top_module */
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module_manager.add_child_module(top_module, cb_module);
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/* Set an unique name to the instance
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* Note: it is your risk to gurantee the name is unique!
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*/
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std::string cb_instance_name = generate_connection_block_module_name(cb_type, vtr::Point<size_t>(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)));
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module_manager.set_child_instance_name(top_module, cb_module,
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cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
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cb_instance_name);
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}
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}
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return cb_instance_ids;
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}
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/********************************************************************
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* Print the top-level module for the FPGA fabric in Verilog format
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* This function will
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* 1. name the top-level module
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* 2. include dependent netlists
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* - User defined netlists
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* - Auto-generated netlists
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* 3. Add the submodules to the top-level graph
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* 4. Add module nets to connect datapath ports
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* 5. Add module nets/submodules to connect configuration ports
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*******************************************************************/
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int build_top_module(ModuleManager& module_manager,
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DecoderLibrary& decoder_lib,
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std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
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const CircuitLibrary& circuit_lib,
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const VprDeviceAnnotation& vpr_device_annotation,
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const DeviceGrid& grids,
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const TileAnnotation& tile_annotation,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const TileDirect& tile_direct,
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const ArchDirect& arch_direct,
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const ConfigProtocol& config_protocol,
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const CircuitModelId& sram_model,
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const bool& frame_view,
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const bool& compact_routing_hierarchy,
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const bool& duplicate_grid_pin,
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const FabricKey& fabric_key,
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const bool& generate_random_fabric_key) {
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vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
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int status = CMD_EXEC_SUCCESS;
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/* Create a module as the top-level fabric, and add it to the module manager */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.add_module(top_module_name);
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/* Label module usage */
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module_manager.set_module_usage(top_module, ModuleManager::MODULE_TOP);
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std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
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/* Add sub modules, which are grid, SB and CBX/CBY modules as instances */
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/* Add all the grids across the fabric */
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vtr::Matrix<size_t> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, grids);
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/* Add all the SBs across the fabric */
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vtr::Matrix<size_t> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, device_rr_gsb, compact_routing_hierarchy);
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/* Add all the CBX and CBYs across the fabric */
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cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy);
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cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy);
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/* Add nets when we need a complete fabric modeling,
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* which is required by downstream functions
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*/
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if (false == frame_view) {
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/* Reserve nets to be memory efficient */
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reserve_module_manager_module_nets(module_manager, top_module);
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/* Add module nets to connect the sub modules */
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add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module,
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vpr_device_annotation,
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grids, grid_instance_ids,
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rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids,
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compact_routing_hierarchy, duplicate_grid_pin);
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/* Add inter-CLB direct connections */
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add_top_module_nets_tile_direct_connections(module_manager, top_module, circuit_lib,
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vpr_device_annotation,
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grids, grid_instance_ids,
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tile_direct, arch_direct);
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}
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/* Add global ports from grid ports that are defined as global in tile annotation */
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status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, vpr_device_annotation, grids, grid_instance_ids);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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/* Add GPIO ports from the sub-modules under this Verilog module
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* This is a much easier job after adding sub modules (instances),
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* we just need to find all the I/O ports from the child modules and build a list of it
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*/
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add_module_gpio_ports_from_child_modules(module_manager, top_module);
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/* Organize the list of memory modules and instances
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* If we have an empty fabric key, we organize the memory modules as routine
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* Otherwise, we will load the fabric key directly
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*/
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if (true == fabric_key.empty()) {
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organize_top_module_memory_modules(module_manager, top_module,
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circuit_lib, config_protocol, sram_model,
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grids, grid_instance_ids,
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device_rr_gsb, sb_instance_ids, cb_instance_ids,
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compact_routing_hierarchy);
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} else {
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VTR_ASSERT_SAFE(false == fabric_key.empty());
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/* Throw a fatal error when the fabric key has a mismatch in region organization.
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* between architecture file and fabric key
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*/
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if (size_t(config_protocol.num_regions()) != fabric_key.regions().size()) {
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VTR_LOG_ERROR("Fabric key has a different number of configurable regions (='%ld') than architecture definition (=%d)!\n",
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fabric_key.regions().size(),
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config_protocol.num_regions());
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return CMD_EXEC_FATAL_ERROR;
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}
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status = load_top_module_memory_modules_from_fabric_key(module_manager, top_module,
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circuit_lib, config_protocol,
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fabric_key);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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}
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/* Shuffle the configurable children in a random sequence */
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if (true == generate_random_fabric_key) {
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shuffle_top_module_configurable_children(module_manager, top_module, config_protocol);
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}
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/* Add shared SRAM ports from the sub-modules under this Verilog module
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* This is a much easier job after adding sub modules (instances),
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* we just need to find all the I/O ports from the child modules and build a list of it
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*/
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size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module);
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if (0 < module_num_shared_config_bits) {
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add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits);
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}
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/* Add SRAM ports from the sub-modules under this Verilog module
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* This is a much easier job after adding sub modules (instances),
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* we just need to find all the I/O ports from the child modules and build a list of it
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*/
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TopModuleNumConfigBits top_module_num_config_bits = find_top_module_regional_num_config_bit(module_manager, top_module, circuit_lib, sram_model, config_protocol.type());
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if (!top_module_num_config_bits.empty()) {
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add_top_module_sram_ports(module_manager, top_module,
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circuit_lib, sram_model,
|
|
config_protocol,
|
|
top_module_num_config_bits);
|
|
}
|
|
|
|
/* Add module nets to connect memory cells inside
|
|
* This is a one-shot addition that covers all the memory modules in this pb module!
|
|
*/
|
|
if (0 < module_manager.configurable_children(top_module).size()) {
|
|
add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks,
|
|
top_module,
|
|
circuit_lib,
|
|
config_protocol, circuit_lib.design_tech_type(sram_model),
|
|
top_module_num_config_bits);
|
|
}
|
|
|
|
/* Add global ports to the top module:
|
|
* This is a much easier job after adding sub modules (instances),
|
|
* we just need to find all the global ports from the child modules and build a list of it
|
|
* @note This function is called after the add_top_module_nets_memory_config_bus() because it may add some sub modules
|
|
*/
|
|
add_module_global_ports_from_child_modules(module_manager, top_module);
|
|
|
|
return status;
|
|
}
|
|
|
|
} /* end namespace openfpga */
|