tangxifan f456c7e236 [Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules		2021-09-29 20:34:25 -07:00
..
annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators	2021-09-29 20:21:46 -07:00
fabric	[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules	2021-09-29 20:34:25 -07:00
fpga_bitstream	[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs	2021-09-25 20:22:27 -07:00
fpga_sdc	Merge branch 'master' into dev	2021-06-23 09:15:03 -06:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator	2021-09-25 19:34:21 -07:00
mux_lib	[Engine] Support WLR port in OpenFPGA architecture file and fabric generator	2021-09-20 16:05:36 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP	2021-09-28 17:29:03 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00