tangxifan 04594cb7ab [Test] Adapt bitstream annotatin file to parser's requirement		2021-02-01 17:38:36 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script	2021-02-01 12:05:04 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	[Arch] Decide to move external bitstream definition to a separated XML file	2021-02-01 15:57:44 -07:00
openfpga_cell_library	[HDL] Bug fix in HDL netlist due to port name mismatching	2021-02-01 11:35:25 -07:00
openfpga_shell_scripts	[Script] Now multi-clock openfpga shell script no longer needs activity file	2021-01-29 11:40:33 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Regression] Upgraded runtime enviroment to python3.8	2021-01-26 16:40:45 -07:00
tasks	[Test] Adapt bitstream annotatin file to parser's requirement	2021-02-01 17:38:36 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Bug fix in architecture. Now soft adder modes are accepted	2021-02-01 13:43:39 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00