tangxifan 430580f138 [HDL] Fix a typo		2022-02-15 16:09:14 -08:00
..
counter_4bit_2clock	[HDL] Fix a typo	2022-02-15 16:09:14 -08:00
counter_8bit_async_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_8bit_async_resetb	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_8bit_sync_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_128bit_async_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_128bit_async_resetb	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00