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build_decoder_modules.cpp
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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build_decoder_modules.h
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add decoder module builders
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2019-10-18 21:01:10 -06:00 |
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build_device_module.cpp
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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build_device_module.h
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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build_essential_modules.cpp
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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build_essential_modules.h
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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build_grid_modules.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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build_grid_modules.h
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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build_lut_modules.cpp
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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build_lut_modules.h
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add lut module generation and simplify Verilog generation codes
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2019-10-21 17:54:15 -06:00 |
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build_memory_modules.cpp
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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build_memory_modules.h
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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build_module_graph_utils.cpp
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add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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build_module_graph_utils.h
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add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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build_mux_modules.cpp
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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build_mux_modules.h
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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build_routing_modules.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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build_routing_modules.h
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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build_top_module.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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build_top_module.h
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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build_top_module_directs.cpp
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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build_top_module_directs.h
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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build_top_module_memory.cpp
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added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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build_top_module_memory.h
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add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
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build_wire_modules.cpp
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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build_wire_modules.h
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add wire module generation and simplify Verilog generation for wires
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2019-10-21 20:20:34 -06:00 |
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