tangxifan e7f2bd3b7c Merge branch 'multimode_clb' into tileable_routing		2019-06-19 21:31:54 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	Merge branch 'multimode_clb' into tileable_routing	2019-06-19 21:31:54 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Update regression test avoiding overwritting files	2019-06-14 11:44:44 -06:00
CMakeLists.txt	fix CMakeList bug in disabling VPR graphics	2019-06-15 13:21:25 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	rename rr_switch_block to rr_gsb, a generic block	2019-06-06 17:41:01 -06:00
regression_verilog.sh	bug fixing for memory leaking in allocating pb_rr_graph and power estimation	2019-06-15 12:23:36 -06:00