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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice
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Aur??Lien ALACCHI de2bc18bbb bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
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base support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
clb_pin_remap rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
spice bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
verilog bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00