tangxifan c6ac02d210 [FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation		2020-09-20 15:21:33 -06:00
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src	[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation	2020-09-20 15:21:33 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	now inout must be global port and I/O port so that it will appear in the top-level module	2020-04-08 16:54:08 -06:00
test_script	bug fix in pnr sdc grid writer for module paths in hierarchical view	2020-06-11 19:31:05 -06:00
test_vpr_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
CMakeLists.txt	remove obselete codes and update regression tests	2020-07-04 17:31:34 -06:00