Ganesh Gore da0778e813 Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev		2019-11-01 00:46:34 -06:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	single mode is working, multi-mode is under debugging	2019-10-29 22:32:36 -06:00
arch	single mode is working, multi-mode is under debugging	2019-10-29 22:32:36 -06:00
benchmarks	adding mcnc_big20 to regression test	2019-10-31 19:31:27 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Updated formality python script	2019-09-27 14:00:57 -06:00
scripts	Bug fix: Missing exit_if_fail flag in fpga_flow script	2019-10-31 09:56:57 -06:00
tasks	adding more regression tests which is quick run but very helpful for debugging	2019-10-31 20:17:40 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00