Go to file
tangxifan d96ffdc00c [Doc] Bug fix in importing imgconverter package 2021-02-07 11:52:04 -07:00
.github [Test] Add new test case to CI script 2021-02-01 11:16:12 -07:00
abc Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
ace2 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docker Bug fix on Docker build and upload on master (#202) 2021-01-29 11:16:57 -07:00
docs [Doc] Bug fix in importing imgconverter package 2021-02-07 11:52:04 -07:00
libopenfpga [Tool] Remove redundant tab in bitstream setting writer 2021-02-01 18:04:21 -07:00
libs [Tool] Patch to remove compiler warnings 2021-02-04 16:54:04 -07:00
openfpga [Tool] Add bitstream annotation support 2021-02-01 20:49:36 -07:00
openfpga_flow Merge pull request #217 from lnis-uofu/dev 2021-02-05 09:53:28 -07:00
vpr [Tool] Borrow a quick fix from the VPR pull request https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files 2021-02-04 17:30:49 -07:00
yosys@1fafc16a25 Bumping up latest yosys changes related to adder tech mapping 2021-02-03 14:30:06 +05:30
.dockerignore Bug fix on Docker build and upload on master (#202) 2021-01-29 11:16:57 -07:00
.gitignore Github action optimizations 2020-12-10 14:35:19 -07:00
.gitmodules Removing yosys-symbiflow-plugins submodule and will be added separately later via another PR 2020-12-10 21:06:08 -08:00
.readthedocs.yml [Doc] Add readthedoc setting file 2020-11-12 19:43:43 -07:00
CMakeLists.txt Removing yosys-symbiflow-plugins compilation from CMakefile 2020-12-10 21:44:57 -08:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile Adding target compile in Makefile that just compiles without updating submodules 2020-12-14 09:25:50 -08:00
README.md [Doc] Add tutorial video link to front-page 2021-02-06 17:15:53 -07:00
openfpga.sh [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
requirements.txt [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

If this is the first time you learn OpenFPGA, we strongly recommend you to watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users to checkout the summary of technical capabilities before compiling.

Compilation

A tutorial video about how-to-compile can be found here

Before start, we strongly recommend you to read the required dependencies at compilation guidelines. It also includes detailed information about docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.

python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find some tutorials in the ./tutorials folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.