tangxifan 79fa858f36 remove unused ports for Verilog modules		2019-09-11 19:39:59 -06:00
..
SRC	remove unused ports for Verilog modules	2019-09-11 19:39:59 -06:00
CMakeLists.txt	start creating the class for circuit models	2019-08-07 11:38:45 -06:00
config_basic_arch.xml	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
ctags_libarchfpga_src.sh	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
libarchfpga.vcxproj	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
libarchfpga.vcxproj.filters	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
tags	Latest version, not stable yet but close	2019-07-09 08:34:01 -06:00