127 lines
3.6 KiB
C++
127 lines
3.6 KiB
C++
/******************************************************************************
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* Memember functions for data structure FabricVerilogOption
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******************************************************************************/
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#include "vtr_assert.h"
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#include "verilog_options.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/**************************************************
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* Public Constructors
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*************************************************/
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FabricVerilogOption::FabricVerilogOption() {
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output_directory_.clear();
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support_icarus_simulator_ = false;
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include_signal_init_ = false;
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include_timing_ = false;
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explicit_port_mapping_ = false;
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compress_routing_ = false;
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print_top_testbench_ = false;
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print_formal_verification_top_netlist_ = false;
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reference_verilog_file_path_.clear();
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print_user_defined_template_ = false;
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verbose_output_ = false;
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}
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/**************************************************
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* Public Accessors
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*************************************************/
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std::string FabricVerilogOption::output_directory() const {
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return output_directory_;
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}
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bool FabricVerilogOption::support_icarus_simulator() const {
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return support_icarus_simulator_;
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}
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bool FabricVerilogOption::include_timing() const {
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return include_timing_;
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}
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bool FabricVerilogOption::include_signal_init() const {
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return include_signal_init_;
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}
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bool FabricVerilogOption::explicit_port_mapping() const {
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return explicit_port_mapping_;
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}
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bool FabricVerilogOption::compress_routing() const {
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return compress_routing_;
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}
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bool FabricVerilogOption::print_top_testbench() const {
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return print_top_testbench_;
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}
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bool FabricVerilogOption::print_formal_verification_top_netlist() const {
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return print_formal_verification_top_netlist_;
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}
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bool FabricVerilogOption::print_autocheck_top_testbench() const {
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return false == reference_verilog_file_path_.empty();
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}
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std::string FabricVerilogOption::reference_verilog_file_path() const {
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return reference_verilog_file_path_;
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}
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bool FabricVerilogOption::print_user_defined_template() const {
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return print_user_defined_template_;
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}
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bool FabricVerilogOption::verbose_output() const {
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return verbose_output_;
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}
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/******************************************************************************
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* Private Mutators
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******************************************************************************/
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void FabricVerilogOption::set_output_directory(const std::string& output_dir) {
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output_directory_ = output_dir;
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}
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void FabricVerilogOption::set_support_icarus_simulator(const bool& enabled) {
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support_icarus_simulator_ = enabled;
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}
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void FabricVerilogOption::set_include_timing(const bool& enabled) {
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include_timing_ = enabled;
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}
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void FabricVerilogOption::set_include_signal_init(const bool& enabled) {
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include_signal_init_ = enabled;
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}
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void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
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explicit_port_mapping_ = enabled;
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}
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void FabricVerilogOption::set_compress_routing(const bool& enabled) {
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compress_routing_ = enabled;
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}
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void FabricVerilogOption::set_print_top_testbench(const bool& enabled) {
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print_top_testbench_ = enabled;
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}
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void FabricVerilogOption::set_print_formal_verification_top_netlist(const bool& enabled) {
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print_formal_verification_top_netlist_ = enabled;
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}
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void FabricVerilogOption::set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path) {
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reference_verilog_file_path_ = reference_verilog_file_path;
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}
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void FabricVerilogOption::set_print_user_defined_template(const bool& enabled) {
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print_user_defined_template_ = enabled;
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}
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void FabricVerilogOption::set_verbose_output(const bool& enabled) {
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verbose_output_ = enabled;
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}
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} /* end namespace openfpga */
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