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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan c6c3ef71f3 adapt all the Verilog submodule writers and bring it onlien 2020-02-16 13:35:18 -07:00
tangxifan 4cb61e2138 bring preprocessing flag Verilog netlists online 2020-02-16 00:03:24 -07:00
tangxifan bf54be3d00 add option data structure for FPGA Verilog 2020-02-15 21:39:47 -07:00