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OpenFPGA
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tangxifan d391983e8c passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
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SpiceNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
VerilogNetlists passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
arch passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
benchmarks passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
docs Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
misc Added Modelsim Python Script 2019-11-01 18:20:40 -06:00
scripts Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
tasks add test for heterogeneous FPGA and fix bugs 2019-11-06 17:45:11 -07:00
tech Added Power Model Files 2019-08-19 18:55:23 -06:00
.gitignore Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00