tangxifan 51e1547634 [test] hotfix		2023-06-26 15:32:16 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
openfpga_arch	[test] add a new testcase for subtile and deploy it to basic regression test	2023-05-03 15:41:29 +08:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] add a new testcase to validate mock wrapper	2023-06-26 15:26:50 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches	2023-06-25 22:49:51 -07:00
scripts	[test] reworking adder mapping flow to validate carry chain mapping	2023-06-20 16:57:08 -07:00
tasks	[test] hotfix	2023-06-26 15:32:16 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[arch] fixed a bug where the array size mismatch the layout name	2023-05-03 22:23:20 +08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00