tangxifan cec6bf0b6f add or2 microbenchmark for testing external arch bitstream		2020-07-27 15:59:03 -06:00
..
OpenFPGAShellScripts	add load architecture bitstream test case and reorganize regression tests in category of openfpga tools	2020-07-27 15:54:46 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
arch_bitstreams	add load architecture bitstream test case and reorganize regression tests in category of openfpga tools	2020-07-27 15:54:46 -06:00
benchmarks	add or2 microbenchmark for testing external arch bitstream	2020-07-27 15:59:03 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	update fabric key to synchronize with new module/instance naming	2020-07-24 12:55:40 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	update openfpga architecture README for power-gating	2020-07-22 21:55:59 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	TASK_NAME and TASK_DIR variables are avaialble in config file now	2020-07-27 14:14:57 -06:00
tasks	add or2 microbenchmark for testing external arch bitstream	2020-07-27 15:59:03 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	use k6_n10 architecture to reduce CI runtime	2020-07-22 13:45:55 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00