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behavioral_verilog/config
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2020-07-27 15:25:49 -06:00 |
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benchmark_sweep
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2020-07-27 15:25:49 -06:00 |
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bram
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2020-07-27 15:25:49 -06:00 |
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compilation_verification/config
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2020-07-27 15:25:49 -06:00 |
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depopulate_crossbar/config
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2020-07-27 15:25:49 -06:00 |
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duplicated_grid_pin/config
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2020-07-27 15:25:49 -06:00 |
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fabric_chain
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2020-07-27 15:25:49 -06:00 |
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fabric_key
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2020-07-27 15:25:49 -06:00 |
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fixed_simulation_settings/config
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2020-07-27 15:25:49 -06:00 |
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flatten_routing/config
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2020-07-27 15:25:49 -06:00 |
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fpga_bitstream
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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fpga_spice/generate_spice/config
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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full_testbench
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2020-07-27 15:25:49 -06:00 |
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generate_fabric/config
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2020-07-27 15:25:49 -06:00 |
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generate_testbench/config
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2020-07-27 15:25:49 -06:00 |
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hard_adder/config
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2020-07-27 15:25:49 -06:00 |
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implicit_verilog/config
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2020-07-27 15:25:49 -06:00 |
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io
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2020-07-27 15:25:49 -06:00 |
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lut_design
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2020-07-27 15:25:49 -06:00 |
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mcnc_big20/config
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2020-07-27 15:25:49 -06:00 |
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mux_design
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2020-07-27 15:25:49 -06:00 |
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ncounter/config
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2020-07-27 15:25:49 -06:00 |
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power_gated_design/power_gated_inverter/config
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2020-07-27 15:25:49 -06:00 |
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preconfig_testbench
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2020-07-27 15:25:49 -06:00 |
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sdc_time_unit/config
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2020-07-27 15:25:49 -06:00 |
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spypad/config
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2020-07-27 15:25:49 -06:00 |
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untileable/config
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2020-07-27 15:25:49 -06:00 |
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.gitignore
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Added gitignore to skip run directory tracking
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2019-08-19 19:06:01 -06:00 |
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generate_testbenches
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Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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