tangxifan 71ad0721a1 Merge branch 'master' into vtr_upgrade		2022-08-31 13:56:17 -07:00
..
basic_reg_test.sh	Merge branch 'master' into vtr_upgrade	2022-08-31 13:56:17 -07:00
basic_reg_yosys_only_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
fpga_bitstream_reg_test.sh	[test] now add QuickLogic memory bank to fpga bitstream regression tests	2022-05-25 11:42:32 +08:00
fpga_sdc_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
fpga_spice_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
fpga_verilog_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
iwls_benchmark_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
micro_benchmark_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
quicklogic_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00
vtr_benchmark_reg_test.sh	[test] now regression test script supports remove all run dir through command-line options	2022-05-22 13:15:39 +08:00