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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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bdc13e491e
OpenFPGA
/
openfpga_flow
/
tasks
/
fpga_bitstream
/
generate_bitstream
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tangxifan
efc9bf9907
[test] added new test case to validate bitstream generation
2023-06-19 12:40:37 -07:00
..
configuration_chain
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
2022-05-25 11:19:49 +08:00
fpga_core_wrapper
/config
[test] added new test case to validate bitstream generation
2023-06-19 12:40:37 -07:00
ql_memory_bank_shift_register
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00