OpenFPGA/openfpga_flow/regression_test_scripts
tangxifan 15a8d8a76a [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation 2023-08-18 21:59:06 -07:00
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basic_reg_test.sh [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation 2023-08-18 21:59:06 -07:00
basic_reg_yosys_only_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
fpga_bitstream_reg_test.sh [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
fpga_sdc_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
fpga_spice_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
fpga_verilog_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
iwls_benchmark_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
micro_benchmark_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
quicklogic_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
tcl_reg_test.sh [script] enable eval mode in tcl reg test 2022-12-02 12:07:27 -08:00
vtr_benchmark_reg_test.sh [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00