tangxifan b3796b0818 build io location map		2020-02-26 19:58:18 -07:00
..
annotation	add more methods to acquire physical truth table from physical pb	2020-02-25 21:21:44 -07:00
base	build io location map	2020-02-26 19:58:18 -07:00
fabric	build io location map	2020-02-26 19:58:18 -07:00
fpga_bitstream	debugged LUT bitstream	2020-02-26 11:42:18 -07:00
fpga_verilog	add io location map data structure and start porting verilog testbench generator	2020-02-26 17:10:57 -07:00
mux_lib	add mux library builder	2020-02-12 14:58:23 -07:00
repack	debugged LUT bitstream	2020-02-26 11:42:18 -07:00
tile_direct	tile direct supports inter-column/inter-row direct connections	2020-02-15 13:42:53 -07:00
utils	found the bug in physical pb mode bits and fixed	2020-02-25 23:45:49 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start working on repack	2020-02-17 17:57:43 -07:00