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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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b330fb4bb7
OpenFPGA
/
vpr7_x2p
/
vpr
History
Baudouin Chauviere
c4b42726c4
fixes easing thehandling by the user.
2019-03-31 07:55:05 -06:00
..
ARCH
fixa bug in determining mux structure
2019-01-22 13:54:50 -07:00
Circuits
Add new benchmark and modify go.sh to use it
2018-12-26 04:24:26 -07:00
SRC
Update rr_graph_area.c
2019-03-11 21:46:42 +08:00
SpiceNetlists
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
VerilogNetlists
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
picorv
Changed for the naming
2018-12-08 16:19:38 -07:00
Makefile
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
go.sh
fixes easing thehandling by the user.
2019-03-31 07:55:05 -06:00
picorv.sh
Changed for the naming
2018-12-08 16:19:38 -07:00