tangxifan 129caea38c [Architecture] Patch configurable latch Verilog HDL with resetb		2020-09-23 18:30:48 -06:00
..
OpenFPGAShellScripts	[Regression Test] Add a new template script for fixed device support	2020-09-23 16:46:41 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	[Architecture] Patch configurable latch Verilog HDL with resetb	2020-09-23 18:30:48 -06:00
arch_bitstreams	add load architecture bitstream test case and reorganize regression tests in category of openfpga tools	2020-07-27 15:54:46 -06:00
benchmarks	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	update fabric key to synchronize with new module/instance naming	2020-07-24 12:55:40 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	[Architecture] Bug fix in configurable latch Verilog HDL	2020-09-23 18:28:45 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	now pro_blif.pl can accept customized clock name	2020-08-19 09:43:44 -06:00
tasks	[Architecture] Use strict latch Verilog HDL in frame-based procotol	2020-09-23 17:58:13 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Architecture] Add k4 series architecture using pattern-based local routing	2020-09-23 16:05:39 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00