OpenFPGA/vpr7_x2p/vpr/SRC/device/rr_graph
tangxifan 4cffd8ac2d keep route file updated with tileable rr_graph 2019-08-13 15:37:42 -06:00
..
chan_node_details.cpp bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
chan_node_details.h many bug fixing for tileable rr_graph generator. Still debugging 2019-06-21 17:58:46 -06:00
gsb_graph.cpp start building object GSB graph 2019-06-17 22:10:30 -06:00
gsb_graph.h start building object GSB graph 2019-06-17 22:10:30 -06:00
rr_graph_builder_utils.cpp keep route file updated with tileable rr_graph 2019-08-13 15:37:42 -06:00
rr_graph_builder_utils.h keep route file updated with tileable rr_graph 2019-08-13 15:37:42 -06:00
rr_graph_fwd.h fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tileable_chan_details_builder.cpp add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tileable_chan_details_builder.h add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tileable_rr_graph_builder.cpp bug fixed for the tileable RR graph generator for heterogeneous blocks 2019-07-11 21:02:09 -06:00
tileable_rr_graph_builder.h add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tileable_rr_graph_gsb.cpp bug fixing in Fc_in and be serious in the performance of rr_graph 2019-07-05 16:23:15 -06:00
tileable_rr_graph_gsb.h add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00