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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
History
tangxifan aac4ccb279 fixing bug for heterogeneous FPGAs 2019-11-06 11:19:17 -07:00
..
base fixing bug for heterogeneous FPGAs 2019-11-06 11:19:17 -07:00
bitstream fixing bug for heterogeneous FPGAs 2019-11-06 11:19:17 -07:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
module_builder fixing bug for heterogeneous FPGAs 2019-11-06 11:19:17 -07:00
router fixed bugs in configure pb_rr_graph and dependence on testbenches 2019-08-16 18:20:30 -06:00
shell added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
spice Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
verilog fixing bug for heterogeneous FPGAs 2019-11-06 11:19:17 -07:00