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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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aa070b2a41
OpenFPGA
/
vpr7_x2p
/
vpr
/
SRC
/
fpga_x2p
History
tangxifan
2a3950470e
remove redudant net source addition in cbs and sbs
2020-01-08 19:43:53 -07:00
..
backend_assistant
remove unused codes and parameters
2019-12-24 20:43:29 -07:00
base
remove redudant net source addition in cbs and sbs
2020-01-08 19:43:53 -07:00
bitstream
critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
2019-11-08 15:01:30 -07:00
clb_pin_remap
cleaned unused variables
2019-05-13 14:45:02 -06:00
module_builder
remove redudant net source addition in cbs and sbs
2020-01-08 19:43:53 -07:00
router
fixed bugs in configure pb_rr_graph and dependence on testbenches
2019-08-16 18:20:30 -06:00
shell
deleting legacy codes: fpga_verilog top-level function
2019-12-04 15:55:16 -07:00
spice
Rename SCFF to CCFF, configuration chain flip flop
2019-09-26 11:32:57 -06:00
verilog
remove redudant net source addition in cbs and sbs
2020-01-08 19:43:53 -07:00